Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

Abstract

Abstract-As process, temperature and voltage variations become significant in deep submicron design, timing closure becomes a critical challenge using synchronous CAD flows. One attractive alternative is to use robust asynchronous circuits which gracefully accommodate timing discrepancies. However, these asynchronous circuits typically suffer from high area and latency overhead. In this paper, an optimization algorithm is presented which reduces the area and delay of these circuits by relaxing their overly-restrictive style. The algorithm was implemented and experiments performed on a subset of MCNC circuits. On average, 49.2% of the gates could be implemented in a relaxed manner, 34.9% area improvement was achieved, and 16.1% delay improvement was achieved using a simple heuristic for targeting the critical path in the circuit. This is the first proposed approach that systematically optimizes asynchronous circuits based on the notion of local relaxation while still preserving the circuit's overall timing-robustness.

Low power self-timed carry lookahead adders

“…The RCLA module and adder both correspond to 'early output logic' [9] [10], i.e., the dual-rail carry and sum outputs may be reset in an eager fashion (eager reset) based on a subset of the inputs becoming spacers, while early set does not occur. Early output logic could generally help in reducing area, delay and/or power metrics [9] [10] [12]. The completion detection circuit [5] [10], present before the combinational adder logic, is assigned the responsibility of indicating the arrival of all the primary inputs, and hence isochronic fork assumptions are made with respect to all the primary inputs.…”

“…Similarly, an unacknowledged wire transition called as wire orphan should also be eliminated. The avid reader is directed to [10] [12] for an explanation of gate and wire orphans; the details are omitted here for brevity. The critical (carry) propagation path in the CLA modules is represented by either of the curved arrows in Figure 1(b).…”

M-of-N Code Decomposition for Indicating Combinational Logic

“…Figure 5 shows such a rectangle, the two sub-rectangles are shaded in different shades. The rectangles intersect in code-word d 6 .…”

Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks

“…This approach allows large self-timed datapaths to be constructed relatively easily. Furthermore, several recent techniques have been developed that significantly reduce the cost (in area, power and delay) of the initial network by using techniques such as weak-indication [4] [19] and relative timing [3].…”

“…The cost functions of the UCP solvers use a simple metric based on literal counts in order to maximise the number of don't care values that may be exploited by multilevel optimisation. It is possible to use more complex cost functions (such as those used in the UCP-based desynchronisation optimisation techniques [4][5] [19]) if physical implementations are targeted.…”