One of the popular methods of asynchronous logic implementation is based on so called Delay-Insensitive-Minterm-System (DIMS), where a sum-of-minterms (SOM) function is given and each minterm is represented using a state-holding (C-) element. However, such implementation is rather expensive since minterm minimization is not allowed. In the paper, structure called factorized DIMS is proposed. It is shown that under realistic delay limitation, instead of SOM, strong indication can be ensured for the sum of mutually orthogonal product terms resolved into factorized form. It reduces significant implementation complexity.

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Abstract-Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementation of the functional and completion detection logics, what simplifies the design process; 3) circuit output latency is based on the actual gate delays of the unbounded nature; 4) absence of additional synchronization chains (even of a local nature). However, the area and speed penalty is rather high. In contrast to the state-of-the-art approaches, where simple (NAND, NOR, etc.) 2-input gates are used, we propose a synthesis method based on complex nodes, i.e., nodes implementing any function of an arbitrary number of inputs. Synchronous synthesis procedures may be freely adopted for this purpose. Numerous experiments on standard benchmarks were performed and the efficiency of the proposed complex gate based method is clearly shown. DIMS and Direct Logic based asynchronous designs are considered in the paper.

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