Asynchronous Logic Implementation Based on Factorized DIMS

Lemberski, Igor

doi:10.1142/s0218126617500876

Cited by 6 publications

(50 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Any unacknowledged signal transition on a gate output is termed as gate orphan. The issue of gate orphan has been clearly explained in [33] [34], and the gate orphan problem inherent in [4] shall be explained with the same example circuit that was considered for illustration in [4].…”

Section: Gate Orphan Problem With the Fdims Approach Of [4]mentioning

confidence: 99%

“…Moreover, there exists safe asynchronous strong-and weak-indication combinational logic synthesis methods [6 -8] and [17 -20] which were neither cited nor taken up for comparison in [4]. Further, [4] also embeds a confusion with respect to estimation of the synthesis cost of the resulting solution. In this regard, this paper describes the major problems with [4].…”

Section: Introductionmentioning

confidence: 99%

“…This is because logic factorization can be performed in different ways [12] [13], and most of the conventional factorization techniques cannot be termed as safe for QDI logic synthesis and/or optimization [7] [14]. Nonetheless, without a generic logic synthesis algorithm, it would be difficult for a researcher to be able to reproduce the research presented in [4] and/or verify the correctness of the results reported.…”

Section: Introductionmentioning

confidence: 99%

“…There are two main problematic issues with [4] which will be described in this report. Firstly, in Section 4 of [4], at the beginning of the first paragraph, the author states "To reduce DIMS complexity and ensure strong-indication, a method called factorized DIMS (i.e. FDIMS) is proposed".…”

Section: Introductionmentioning

confidence: 99%

“…The robustness of [7] results from the fact that it employs only safe QDI logic decomposition procedures. However, [6] or [7], which are very relevant to [4], were neither cited nor taken up for comparison in [4]. Besides these, there exists other wellestablished works in the literature such as [15] [16] which form important references for robust asynchronous logic synthesis.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Comments on “Asynchronous Logic Implementation Based on Factorized DIMS”

Balasubramanian¹

2018

Preprint

View full text Add to dashboard Cite

with respect to two main problematic issues: i) the gate orphan problem implicit in the factorized DIMS approach discussed in the referenced article which affects its strong-indication, and ii) how the enumeration of product terms to represent the synthesis cost is skewed in the referenced article because the logic expression contains sum of products and also product of sums. It is observed that the referenced article has not provided a general logic synthesis algorithm excepting only an example illustration involving a 3-input AND logic function. The absence of a general logic synthesis algorithm would make it difficult to reproduce the research described in the referenced article. Moreover, the example illustration in the referenced article describes an unsafe logic decomposition which is not suitable for the multi-level synthesis of strong-indication asynchronous circuits. Further, a logic synthesis method which safely decomposes the DIMS solution to synthesize multi-level strong-indication asynchronous circuits is available in the existing literature, which was neither cited nor taken up for comparison in the referenced article, which is another drawback. Subsequently, it is concluded that the referenced article has not advanced existing knowledge in the field but on the contrary, has caused confusions. Hence, in the interest of readers, this paper additionally highlights some important and relevant literature which provide valuable information about robust asynchronous circuit synthesis techniques which employ delay-insensitive codes for data representation and processing and the 4-phase return-to-zero handshake protocol for data communication.

show abstract

Section: Gate Orphan Problem With the Fdims Approach Of [4]mentioning

confidence: 99%