Optimal Two-Level Delay — Insensitive Implementation of Logic Functions

Lemberski, Igor; Josephs, Mark B.

doi:10.1007/3-540-45716-x_10

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2004

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Cited by 2 publications

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“…optimization and transistor reduction; one of the main difficulties is to preserve the property of quasi-delay insensitivity [5][6][7][8][9].…”

mentioning

confidence: 99%

Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits

Folco

Brégier

Fesquet

et al.

Vlsi-Soc: From Systems to Silicon

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WWW home page: http://www.tima.imag.fr/cis in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but do not perform well to automatically synthesize and optimize. This paper presents a new methodology to model and synthesize data path QDI circuits. The model used to represent circuits is based on Multi-valued Decision Diagrams and allows obtaining QDI circuits with two-input gates. Optimization is achieved by applying a technology mapping algorithm with a library of asynchronous standard cells called TAL. This work is a part of the back-end of our synthesis flow from high level language. Throughout the paper, a digit-slice radix 4 ALU is used as an example to illustrate the methodology and show the results.

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“…optimization and transistor reduction; one of the main difficulties is to preserve the property of quasi-delay insensitivity [5][6][7][8][9].…”

mentioning

confidence: 99%