Asynchronous two-level logic of reduced cost

Comments on “Dual-rail asynchronous logic multi-level implementation”

“…Since the synthesis method of [1] is itself shown to be erroneous, the results reported through various Tables in [1] do not carry significance. Nevertheless, on a positive note, the previous work [19] of the authors published in the 2009 DDECS conference constitutes a useful reference for two-level synthesis of arbitrary combinational logic as self-timed circuits.…”

“…Techniques to obtain reduced disjoint sum-of-products (DSOP) for the true and false outputs of a Boolean function, originally expressed in SOP form, based on the ON-set and OFF-set elements inclusive of any don't cares, and their subsequent translation into dual-rail format to implement a combinational logic as a self-timed circuit have been presented in [19,20]. Given this, the first problem of [1], considering the implementation portrayed by Figure 6, is that although [1] states that deriving DSOP form is suitable for self-timed realization of combinational logic, and mentions that it uses the method discussed in [19] for this purpose, reference [1] treats the factorized form of (4) to be a DSOP which is erroneous, and is evident from the gate-level implementation shown in Figure 6. By representing the kernel [a(0) + b(0)] of (4) as 'int1' for our discussion, reference [1] tends to erroneously convey that since F True can be expressed as (int1)c(1) + c(0)d (1), and that the conjunction of these product terms would only yield null, the implementation shown in Figure 6 is therefore a DSOP, and thus satisfies the monotonic cover constraint (MCC) [2].…”

Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes

“…After that each node (both ON-and OFF-sets) can be minimized to reduce the implementation cost. In [Lemberski, 2009], we formulated a minimization constraint that the two-level logic should satisfy, to ensure a hazard-free implementation. Namely, each function y c should be represented as a pair of minimized Sum-of-Products (SOP) forms:…”

“…Our structure is based on the concept of the monotonicity of the nodes introduced in [Cortadella, 2004] and the condition of each two-level (AND-OR) node hazard-free implementation proposed in [Lemberski, 2009]. The node monotonicity is easily achieved by the dual-rail encoding.…”

“…In [Cortadella, 2004], each simple gate is doubled to ensure monotonicity and as a result a hazard-free implementation. In [Lemberski, 2009], a two-level (NOR-NOR, NAND-NAND) dual-rail asynchronous logic suitable for mapping onto the conventional two-level structure was offered. Using this result, we propose a method that is based on the initial logic function decomposition into a single-rail Boolean network, where each node is represented as a two-level logic and the network is further transformation into a dual-rail one to ensure monotonicity and hazard-free implementation.…”