Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes

Lemberski, Igor; Fišer, Petr

doi:10.3182/20091006-3-es-4010.00033

Cited by 3 publications

(4 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…the ones in the on set of the function) are covered exactly once while other minterms (e.g. the ones in the don't care set) can be covered any number of times [10]. In this section we present a general heuristic to efficiently compute a partial DSOP cover.…”

Section: Partial Dsop Synthesismentioning

confidence: 99%

“…DSOP forms can be seen as a special case of partial DSOPs where a subset of minterms of a Boolean function must be covered exactly once, while other minterms can be covered more than once or not be covered at all. In particular this is the case where the points in the on set of a function are covered exactly once, while the points in the don't care set can be covered any number of times [10].…”

Section: Introductionmentioning

confidence: 99%

“…Besides its theoretical interest, DSOP minimization is relevant in the area of digital circuits for determining various properties of Boolean functions and for the synthesis of asynchronous circuits, as discussed for example in [4,10,11,12,16]. DSOPs are indeed used as a starting point for the synthesis of Exclusive-Or-Sum-Of-Products (ESOP) forms, and for calculating the spectra of Boolean functions.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Compact DSOP and Partial DSOP Forms

et al. 2013

View full text Add to dashboard Cite

Given a Boolean function f on n variables, a Disjoint Sum-of-Products (DSOP) of f is a set of products (ANDs) of subsets of literals whose sum (OR) equals f , such that no two products cover the same minterm of f . DSOP forms are a special instance of partial DSOPs, i.e. the general case where a subset of minterms must be covered exactly once and the other minterms (typically corresponding to don't care conditions of f ) can be covered any number of times. We discuss finding DSOPs and partial DSOP with a minimal number of products, a problem theoretically connected with various properties of Boolean functions and practically relevant in the synthesis of digital circuits. Finding an absolute minimum is hard, in fact we prove that the problem of absolute minimization of partial DSOPs is NPhard. Therefore it is crucial to devise a polynomial time heuristic that compares favorably with the known minimization tools. To this end we develop a further piece of theory starting from the definition of the weight of a product p as a functions of the number of fragments induced on other cubes by the selection of p, and show how product weights can be exploited for building a class of minimization heuristics for DSOP and partial DSOP synthesis. A set of experiments conducted on major benchmark functions show that our method, with a family of variants, always generates better results than the ones of previous heuristics, including the method based on a BDD representation of f .

show abstract

Section: Partial Dsop Synthesismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Compact DSOP and Partial DSOP Forms

et al. 2013

View full text Add to dashboard Cite

show abstract

“…In [14], a method was proposed where the initial function is decomposed into a single-rail network of two-level AND-OR nodes first. Then the network is transformed into a dualrail one, to ensure monotonicity and hazard-free implementation.…”

Section: Introductionmentioning

confidence: 99%

Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints

Lemberski

Fišer

2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

Self Cite

View full text Add to dashboard Cite

Abstract-Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementation of the functional and completion detection logics, what simplifies the design process; 3) circuit output latency is based on the actual gate delays of the unbounded nature; 4) absence of additional synchronization chains (even of a local nature). However, the area and speed penalty is rather high. In contrast to the state-of-the-art approaches, where simple (NAND, NOR, etc.) 2-input gates are used, we propose a synthesis method based on complex nodes, i.e., nodes implementing any function of an arbitrary number of inputs. Synchronous synthesis procedures may be freely adopted for this purpose. Numerous experiments on standard benchmarks were performed and the efficiency of the proposed complex gate based method is clearly shown. DIMS and Direct Logic based asynchronous designs are considered in the paper.

show abstract