Comments on “Dual-rail asynchronous logic multi-level implementation”

Balasubramanian, P.

doi:10.1016/j.vlsi.2015.08.001

Cited by 17 publications

(15 citation statements)

References 28 publications

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“…Wire orphans and gate orphans are the two circuit orphans which should be avoided in a QDI circuit as they could affect the robustness [28][29][30], resulting in the circuit becoming non-QDI. For example, referring to Figure 5a, let us assume that after a RTZ phase, all the dual rail inputs of the majority voter have assumed 0, i.e., X1 = X0 = 0, Y1 = Y0 = 0 and Z1 = Z0 = 0.…”

Section: Qdi Tmr Implementationmentioning

confidence: 99%

Quasi Delay Insensitive Majority Voters for Triple Modular Redundancy Applications

2019

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Mission- and safety-critical applications tend to incorporate triple modular redundancy (TMR) in their hardware implementation to reliably withstand the fault or failure of any one of the function modules during normal operation, and the function module may be a circuit or a system. In a TMR implementation, two identical copies of a function module are used in addition to the original function module, and the correct operation of at least two function modules is required. In TMR, the corresponding primary outputs of the three function modules are combined using majority voters, which determine the actual primary outputs based on the Boolean majority. Hence, the majority voter is an important component that is useful for conveying the correct operation of a TMR implementation. In the existing literature, many designs of three-input majority voters for TMR have been discussed. However, most of these correspond to the synchronous design style and just one corresponds to the bundled-data asynchronous design style, which is not delay insensitive and hence non-robust. To our knowledge, a robust delay insensitive design of the three-input majority voter has not been considered. In this context, this article presents the designs of robust quasi delay insensitive (QDI) three-input majority voters based on QDI logic synthesis methods, and analyzes which majority voters are preferable in terms of speed, power, and area. We implement example QDI TMR circuits using a QDI full adder as the function module and QDI majority voters using 32/28 nm complementary metal oxide semiconductor (CMOS) technology. The QDI TMR implementations use the delay insensitive dual rail code for data encoding, and four-phase return-to-zero and four-phase return-to-one handshake protocols for data communication.

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Section: Qdi Tmr Implementationmentioning

confidence: 99%

Quasi Delay Insensitive Majority Voters for Triple Modular Redundancy Applications

2019

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“…QDI circuits are classified as strong-indication, weak-indication and early output circuits [20,21]. The input-output timing correlation of strong-indication, weak-indication and early output circuits are depicted through representative timing diagrams in Figure 2.…”

Section: Classes Of Qdi Circuitsmentioning

confidence: 99%

“…Gate orphans are problematic as they could affect the robustness of QDI circuits and they are better avoided by resorting to safe QDI logic decomposition. For an illustration of circuit orphans (i.e., gate orphans and wire orphans) in input-output mode asynchronous circuits, the interested reader is kindly referred to [21,25]. Relative-timed circuits [26] are also early output circuits but they are not QDI because they tend to incorporate extra timing assumptions in addition to the assumption of isochronic forks, which might be sophisticated to realize.…”

Section: Classes Of Qdi Circuitsmentioning

confidence: 99%

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Early Output Quasi-Delay-Insensitive Array Multipliers

et al. 2019

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Multiplication is a widely used arithmetic operation in microprocessing and digital signal processing applications, and multiplication is realized using a multiplier. This article presents the quasi-delay-insensitive (QDI) early output versions of recently reported indicating asynchronous array multipliers. Delay-insensitive dual-rail encoding is used for data representation and processing, and 4-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols are used for data communication. Many QDI array multipliers were realized using a 32/28 nm complementary metal oxide semiconductor (CMOS) technology. Compared to the optimum indicating array multiplier, the proposed optimum early output array multiplier achieves a 6.2% reduction in cycle time and a 7.4% reduction in power-cycle time product (PCTP) with respect to RTZ handshaking, and a 7.6% reduction in cycle time and an 8.8% reduction in PCTP with respect to RTO handshaking without an increase in the area. The simulation results also convey that the RTO handshaking is preferable to the RTZ handshaking for the optimum implementation of QDI array multipliers.

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“…Any unacknowledged signal transition on a gate output is termed as gate orphan. The issue of gate orphan has been clearly explained in [33] [34], and the gate orphan problem inherent in [4] shall be explained with the same example circuit that was considered for illustration in [4].…”

Section: Gate Orphan Problem With the Fdims Approach Of [4]mentioning

confidence: 99%

Comments on “Asynchronous Logic Implementation Based on Factorized DIMS”

Balasubramanian¹

2018

Preprint

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with respect to two main problematic issues: i) the gate orphan problem implicit in the factorized DIMS approach discussed in the referenced article which affects its strong-indication, and ii) how the enumeration of product terms to represent the synthesis cost is skewed in the referenced article because the logic expression contains sum of products and also product of sums. It is observed that the referenced article has not provided a general logic synthesis algorithm excepting only an example illustration involving a 3-input AND logic function. The absence of a general logic synthesis algorithm would make it difficult to reproduce the research described in the referenced article. Moreover, the example illustration in the referenced article describes an unsafe logic decomposition which is not suitable for the multi-level synthesis of strong-indication asynchronous circuits. Further, a logic synthesis method which safely decomposes the DIMS solution to synthesize multi-level strong-indication asynchronous circuits is available in the existing literature, which was neither cited nor taken up for comparison in the referenced article, which is another drawback. Subsequently, it is concluded that the referenced article has not advanced existing knowledge in the field but on the contrary, has caused confusions. Hence, in the interest of readers, this paper additionally highlights some important and relevant literature which provide valuable information about robust asynchronous circuit synthesis techniques which employ delay-insensitive codes for data representation and processing and the 4-phase return-to-zero handshake protocol for data communication.

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Comments on “Dual-rail asynchronous logic multi-level implementation”

Cited by 17 publications

References 28 publications

Quasi Delay Insensitive Majority Voters for Triple Modular Redundancy Applications

Quasi Delay Insensitive Majority Voters for Triple Modular Redundancy Applications

Early Output Quasi-Delay-Insensitive Array Multipliers

Comments on “Asynchronous Logic Implementation Based on Factorized DIMS”

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