Dual-rail asynchronous logic multi-level implementation

Lemberski, Igor; Fišer, Petr

doi:10.1016/j.vlsi.2013.02.002

Cited by 5 publications

(41 citation statements)

References 23 publications

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“…An exemplar Boolean function (F) implementation has been considered in [1] (refer to Figure 10 in Section 4.4) to illustrate their proposed synthesis method, which is shown as Figure 6 here. Some coloured markings and labels have been introduced to the original Figure 10 of [1], depicted as Figure 6, to aid with further discussions. We shall describe the major/minor problems implicit in the synthesis method of [1] through this illustration.…”

Section: Problems With the Synthesis Methods Of [1]mentioning

confidence: 99%

“…Some coloured markings and labels have been introduced to the original Figure 10 of [1], depicted as Figure 6, to aid with further discussions. We shall describe the major/minor problems implicit in the synthesis method of [1] through this illustration.…”

Section: Problems With the Synthesis Methods Of [1]mentioning

confidence: 99%

“…The minimized sum-of-products (SOP) expression corresponding to the ON-set of the function F viz. F True is given by (1), and the reduced SOP form corresponding to the OFF-set of F viz. F False is given by (2).…”

Section: Problems With the Synthesis Methods Of [1]mentioning

confidence: 99%

“…Let us now assume that a(1) and b(1) are asserted high after a RTZ state, and also assume that c(1) and d(1) are asserted high, but only after a finite time which is equal to the sum of propagation delays of the 2-input AND gate (g11) and the 2-input OR gate (g31). After a(1) and b(1) are defined as 1, X(1) would attain the new value of 1, which implies that gate g11 has acknowledged the arrival of the primary inputs a(1) and b (1). Since X(1) is asserted high, gate g31 eventually produces binary 1 on the primary output Z(1).…”

Section: Early Outputmentioning

confidence: 99%

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Comments on “Dual-rail asynchronous logic multi-level implementation”

Balasubramanian

2016

Integration

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Section: Problems With the Synthesis Methods Of [1]mentioning

confidence: 99%

Section: Problems With the Synthesis Methods Of [1]mentioning

confidence: 99%

Section: Problems With the Synthesis Methods Of [1]mentioning

confidence: 99%

Section: Early Outputmentioning

confidence: 99%

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Comments on “Dual-rail asynchronous logic multi-level implementation”

Balasubramanian

2016

Integration

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“…[5,6]. A look-up table (LUT) is another logic block capable of implementing any function of a given number of variables.…”

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confidence: 99%

LUT‐oriented dual‐rail quasi‐delay‐insensitive logic synthesis

Lemberski

2014

Electron. lett.

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The method of quasi-delay-insensitive logic synthesis using look-up tables (LUTs) is described. It is shown that the dual-rail sum-ofminterm function hazard-free implementation can be done using a single LUT. Namely, instead of the conventional approach based on a DIMS representation where each minterm is implemented on a C-element, the whole sum-of-minterm function is mapped into the single C-element. For Boolean network implementation, it is proved that a fork with branches to different nodes is not required to be isochronic. It simplifies technological synthesis and allows using existing placement and routine methods and tools supposed for synchronous logic. Compared to the conventional approach, the method reduces significantly circuit complexity (in terms of the number of LUTs).Introduction: Delay-insensitive (DI) circuits are a class of asynchronous logic where correct behaviour is independent of gate and wire delays. DI logic is attractive especially for deep-submicron technology where the wire delays may even exceed the gate ones and therefore both types of delays should be taken into account during the design process. Unfortunately, a class of DI circuits is very limited. In practice, DI circuits with the assumption of wire forks are considered. Namely, in any fork, a signal propagates to the end points at the same time. Such a fork is called an isochronic one and the circuits of such a class are called quasi-DI (QDI) ones [1].The state-of-the-art papers in QDI logic design are oriented to implementation using a DIMS [2], direct logic [3], NULL convention logic (NCL) [4] and simple gates (NOR, NAND etc.) [5,6]. A look-up table (LUT) is another logic block capable of implementing any function of a given number of variables. The most popular programmable logic is based on LUTs grouped in configurable logic blocks (CLBs) and wires between the CLBs. Currently, it is supposed for synchronous implementation. Both academic and commercial software tools have been developed. Efforts have been made to develop a special architecture that is suitable for asynchronous implementation [7]. In [8], an approach of asynchronous dual-rail logic synthesis based on XILINX is proposed. It is based on the following: (i) a sum-of-minterm function is described as a DIMS, (ii) each minterm is implemented as a C-element and (iii) a DIMS is decomposed into a Boolean network, where each sub-function is implemented on a single LUT. However, further placement and routine may violate QDI restrictions (isochronic forks) required to ensure hazard-free implementation. The manual correction is done to balance wire delays. Since a formal procedure is not proposed, it is not clear whether or not such a correction is always possible. Our approach differs in the following ways: (i) instead of each minterm implementation, the whole sum-of-minterm dual-rail function is implemented as a C-element and mapped into a single LUT and (ii) the decomposition of a single-rail function is done, and each node is transformed into the dual-rail logic and the...

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Efficient adders for assistive devices

Jhamb

Gitanjali

2017

Engineering Science and Technology, an International Journal

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Dual-rail asynchronous logic multi-level implementation

Cited by 5 publications

References 23 publications

Comments on “Dual-rail asynchronous logic multi-level implementation”

Comments on “Dual-rail asynchronous logic multi-level implementation”

LUT‐oriented dual‐rail quasi‐delay‐insensitive logic synthesis

Efficient adders for assistive devices

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