LUT-Oriented Asynchronous Logic Design Based on Resubstitution

Lemberski, Igor; Suponenkovs, Artjoms; Uhanova, Marina

doi:10.1109/dtis.2019.8734973

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Cited by 2 publications

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“…Note that for these experiments, we did not constraint the number of levels (see for instance i2c levels are increased from 6 to 15). Furthermore, recently, new best-size results have been presented in [44] and [45]. Even though additional size optimizations have been applied on top of our best results, we still hold the best area results for 3 of the results from Table 1, that is, no further optimizations were found for these cases.…”

Section: A Epfl Benchmarksmentioning

confidence: 70%

Extending Boolean Methods for Scalable Logic Synthesis

et al. 2020

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Section: A Epfl Benchmarksmentioning

confidence: 70%

Extending Boolean Methods for Scalable Logic Synthesis

et al. 2020

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“…The window optimization is performed using the resubstitution, which is formulated and solved as a covering task. First time, the resubstitution as the covering task was proposed in Lemberski et al 21 It was oriented on dual-rail (asynchronous) non-scalable (no windowing) design. In this paper, the approach is adapted to synchronous logic scalable optimization.…”

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confidence: 99%

Resubstitution method for big size Boolean logic design targeting look‐up‐table implementation

Lemberski

Suponenkovs

2021

Circuit Theory & Apps

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A scalable design method to perform multilevel network minimization targeting k-input look-up-tables (k-LUT) is proposed. It contributes toward the big size logic design theory and application. The method is based on the resubstitution which is formulated and solved as a covering task: A node function, which depends on an input selected for the resubstitution, is split into a set of dichotomies. The selected input is removed, and the minimal set of inputs to cover the dichotomies are sought. The resubstitution procedure runs on top of the k-LUT network produced by existing synthesis tools (SIS, ABC).Scalability is achieved by the extraction of windows, which satisfy given constraints (number of inputs, nodes, etc.). The window logic is described using the proposed extended programmable logic array (PLA) table, which contains information about don't cares. Experiments show that the best networks obtained using SIS and ABC can be further improved by applying our method. Also, big benchmarks from the EPFL library are processed, and for almost half of them, improvements are achieved.

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LUT-Oriented Asynchronous Logic Design Based on Resubstitution

Cited by 2 publications

References 8 publications

Extending Boolean Methods for Scalable Logic Synthesis

Extending Boolean Methods for Scalable Logic Synthesis

Resubstitution method for big size Boolean logic design targeting look‐up‐table implementation

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