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an optimum cell design without degrading the retention time.A 6F2 single cell (one-cell-per-bit) operation of the floating Operation of FBC and Memory Yield body RAM (FBRAM) is successfully demonstrated for the first time with more than 60% yield of 16Mbit area in a wafer. Fig. 1 shows the operational principle of the FBC. DataThe signal sense margin (SSM) at actual read conditions is states are stored in the form of the floating body potential. To found to well back up the functional results. The parasitic write data "1", by applying a high voltage to the bit-line (BL), resistance in the source and drain formed under the FBC's holes are created by impact ionization and accumulated in the spacers can be optimized for making the SSM as large as floating body. To write data "0", by applying a negative 8gA at ±4.5o without sacrificing the retention time.voltage to the BL, holes are extracted from the body. The stored states can be distinguished using MOSFET current

A 128Mbit FBRAM using the floating body cell(FBC) the size of 0.17µm 2 (6.24F 2 with F=0.165µm) was successfully fabricated and a high bit yield(∼99.999%) was obtained. IntroductionA single transistor gain cell called the floating body cell(FBC) or 1T DRAM cell exploits its floating body formed either on SOI or on bulk silicon as a data storage node [1][2][3]. The elimination of the capacitor from the conventional DRAM cell makes the FBC a half the cell size, a quarter less process cost and easier to be scaled down. We showed the circuit and the device design of a 128Mb DRAM on SOI using the FBC at ISSCC 2005[4] and IEDM 2005[5], respectively. In this paper, we disclose the performance of the floating body random access memory(FBRAM) along with its memory cell's key characteristics. Memory DesignThere are two major issues which are necessary to be addressed in designing a high density FBRAM. One is how to deal with the WL disturb caused by the charge pumping[6] and the other is how to generate an accurate reference voltage to distinguish between the data "1" and "0" for realizing a large scale memory. Fig.1 is a die photo of the 128Mb FBRAM which measures 7.6mm×8.5mm. There are eight 16Mb cell arrays. Fig.2 shows the sense amp.(S/A) circuit including a pMOS current mirror for loading equal current into a data cell and a dummy cell to develop a signal. The holes lost in each WL cycle by the charge pumping(2-3 holes on the average) are replenished by a short and weak restore operation performed by using SAP, while a selected S/A is driven by write column select line(WCSL) between VBLH(BL high level for "1" write) and VBLL(BL low level for "0" write) during write. To generate an accurate reference voltage(Vref) for sensing the data correctly, we adopted a multi-averaging scheme which short circuits 128 pairs of "1" and "0" dummy cells (Fig.3) in parallel(PAV) or in series(SAV). The standard deviation of Vref is expected to be narrowed to σ/(256) 0.5 ideally, where σ stands for the standard deviation of cells' Vth distribution. This RBRAM has a test mode which directly monitors every cell's read current at I/O pads. By entering this test mode(ICMON) after writing "1" or "0", we can measure Ids-Vgs curves of all the memory cells in the chip of the state "1" or "0" by changing the WL voltage in ICMON. Fig.4 shows 1Kb cells' Vth distribution for the both data measured by using ICMON. <∆Vth>=0.35V and σVth0=σVth1=35mV were obtained. Since 32 random fails are fixable by redundancy in every 2Mb segment(±4.17σ), the worst bit-to-bit separation is estimated to be 55mV. As is shown in Fig.5, the number of dummy cells to be effectively averaged in parallel during 20ns signal development time was calculated to be 30(much less than 256) by a Monte Carlo simulation we performed. Since the number of the Vref sets in the segment is 16(±1.5σref), the worst case Vref fluctuation is 3×σref =3×35mV/(30) 0.5 =3×6.4mV=19mV. The sense margin for the both data is calculated to be ∆VS/A=(55mV−19mV)/2=18mV. Fig.6 shows the switching speed m...

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