FBC's Potential of 6F² Single Cell Operation in Multi-Gbit Memories Confirmed by a Newly Developed Method for Measuring Signal Sense Margin

Abstract

an optimum cell design without degrading the retention time.A 6F2 single cell (one-cell-per-bit) operation of the floating Operation of FBC and Memory Yield body RAM (FBRAM) is successfully demonstrated for the first time with more than 60% yield of 16Mbit area in a wafer. Fig. 1 shows the operational principle of the FBC. DataThe signal sense margin (SSM) at actual read conditions is states are stored in the form of the floating body potential. To found to well back up the functional results. The parasitic write data "1", by applying a high voltage to the bit-line (BL), resistance in the source and drain formed under the FBC's holes are created by impact ionization and accumulated in the spacers can be optimized for making the SSM as large as floating body. To write data "0", by applying a negative 8gA at ±4.5o without sacrificing the retention time.voltage to the BL, holes are extracted from the body. The stored states can be distinguished using MOSFET current

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

“…We have developed a novel method of measuring the cell current as a function of RDT. The detail of the method has already been reported [16]. Fig.…”

“…Here we have introduced an index of the signal sense margin (SSM), which predicts the memory chip yield. That is defined as In order to clarify the functionality of the single-cell operation, fail bit count of the 16 Mb area of one chip as a function of WL voltage at read (V WLHR ) as a parameter of read duration time (RDT) has been investigated, which is shown in Fig. 6.…”

“…4 shows a cross-sectional picture of the fabricated memory cell array in the BL direction. Function test with the single-cell operation using dummy cells [13] was carried out for the 16 Mb area under a simple write-read pattern. The results are shown in Fig.…”

“…Some kinds of capacitor-less DRAM cell have been proposed and developed [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. Floating body cell (FBC) is a promising candidate in view of its simple structure and scalability.…”

Optimizing the Readout Bias for the Capacitorless 1T Bulk FinFET RAM Cell

“…Originally, partially depleted silicon-on-insulator (SOI) devices were used to demonstrate the working principle [1]. Later on, more scalable devices were also shown [2]- [4], and in [5] and [6], a 1T-DRAM cell realized on a bulk substrate has also been demonstrated. In particular, bulk FinFET devices are of high interest because they are more scalable than planar bulk devices, have an extra degree of freedom (fin height) for increasing the charge storage area, and can be cointegrated with planar bulk devices and, at the same time, avoid the problem of heat dissipation, which is present in SOI FinFET devices.…”