Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Hamamoto, T.; Ohsawa, Takashi

doi:10.1016/j.sse.2009.03.010

Cited by 20 publications

(7 citation statements)

References 20 publications

(27 reference statements)

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“…We also predict a decrease in the supply voltage to 1.2-1.4V, which is about 25-30% smaller than in current prototypes. Results are in agreement with recent considerations of floating body RAM scaling down to 32nm technology node based on experimental results [8]. …”

Section: Discussionsupporting

confidence: 90%

“…Recently, a revolutionary concept of a DRAM memory cell based on a transistor alone was introduced [1]- [8], and references therein. The ultimate advantage of this new concept is that it does not require a capacitor, and, in contrast to traditional 1T/1C DRAM cells, it thus represents a 1T/0C cell named Z (for zero)-RAM.…”

Section: Introductionmentioning

confidence: 99%

“…While keeping all advantages of the first Z-RAM generation, the most recent generation of Z-RAM cells [9] is characterized by a significantly enlarged programming window and much longer retention times. Recently, a 128Mb floating body RAM was designed and developed [8].…”

Section: Introductionmentioning

confidence: 99%

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Scaling of advanced floating body Z-RAM storage cells: A modeling approach

Sverdlov

Selberherr

2009

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

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A modeling approach to study advanced floating body Z-RAM memory cells is developed. In particular, the scalability of the cells is investigated. First, a Z-RAM cell based on a 50nm gate length double-gate structure corresponding to state of the art technology is studied. A bi-stable behavior essential for Z-RAM operation is observed even in fully depleted structures. It is demonstrated that by adjusting the supply source-drain and gate voltages the programming window can be adjusted. The programming window is appropriately large in voltage as well as in current.We further extend our study to a Z-RAM cell based on an ultra-scaled double-gate MOSFET with 12.5nm gate length. We demonstrate that the cell preserves its functionality by providing a wide voltage operating window with large current differences. An appropriate operating window is still observed at approximately 25-30% reduced supply voltage, which is an additional benefit of scaling. The relation of the obtained supply voltage to the one anticipated in an ultimate MOSFET with quasiballistic transport is discussed.

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Section: Discussionsupporting

confidence: 90%

Section: Introductionmentioning

confidence: 99%

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Scaling of advanced floating body Z-RAM storage cells: A modeling approach

Sverdlov

Selberherr

2009

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

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“…Efforts have been made to find new memory solutions, such as capacitor-less cells [8][9][10]. Floating body based memory structures are among the potential candidates, but impact ionization or band-to-band tunnelling (B2BT) limits their performance [11]. A recently proposed zero impact ionization and zero subthreshold swing device named Z2FET [10,12], has shown significant technology advantages including CMOS technology compatibility, novel capacitor-less memory action and sharp switching characteristics, becomes a promising candidate for capacitor-less DRAM memory cell.…”

Section: Introductionmentioning

confidence: 99%

Thorough Understanding of Retention Time of Z2FET Memory Operation

Duan

Navarro

Cheng³

et al. 2019

IEEE Trans. Electron Devices

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A recently reported zero impact ionization and zero subthreshold swing device Z2FET is a promising candidate for capacitor-less DRAM memory cell. In memory operation, data retention time determines refresh frequency, and is one of the most important memory merits. In this paper, we have systematically investigated the Z2FET retention time based on a newly proposed characterization methodology. It is found that the degradation of HOLD '0' retention time originates from the Gated-SOI portion rather than the Intrinsic-SOI region of the Z2FET. Electrons accumulate under Front Gate (FG) and finally collapse the potential barrier turning logic '0' to '1'. It appears that Shockley-Read-Hall (SRH) generation is the main source for electrons accumulation. Z2FET scalability has been investigated in terms of retention time. As the Z2FET is downscaled, the mechanism dominating electrons accumulation switches from SRH to parasitic injection of electrons from the cathode. Results show that downscaling of Lg has little effect on data '0' retention, but Lin is limited to ~125nm. An optimization method of the fabrication process is proposed based on this new understanding, and Lin can be further scaled down to 75nm. We have demonstrated by 2D TCAD simulation that Z2FET is a promising DRAM cells candidate particularly for IoT applications.

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“…Another expectation is that a cell hit should only disturb cells stored 0s, because a cell hit generates holes in the FB and reinforces cells stored 1s. FB-RAM cells were first realized using partially depleted [5] and fully depleted silicon-on-insulator (SOI) technologies [6]- [8]. The concept has also been demonstrated for devices fabricated on bulk silicon, where the FB is emulated using triple-well isolation [9].…”

Section: Introductionmentioning

confidence: 99%

Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM

Poliakov

Anchlia

Bardon

et al. 2010

IEEE Trans. Circuits Syst. II

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Single-transistor floating-body RAM (FB-RAM) cells present a promising alternative for scalable high-density storage since both access and storage elements are implemented using a single FET-based device. Unlike embedded dynamic RAM (eDRAM) technology, the concept is fully scalable with decreasing technology nodes. However, to make the concept truly usable, special biasing conditions of the device need to be considered; hence, the peripheral elements must be designed accordingly. We propose an approach of FinFET-based cell and peripheral circuit to provide compatible bias conditions for efficient write-read and hold conditions. The periphery is based on the synchronized bit line and word line driver schemes capable of providing compatible voltages to the selected and unselected lines during the different operations. The full circuit has been validated, and the concept has been demonstrated by simulations using the silicon-proven model cards and design decks. Index Terms-BulkFinFET, capacitorless dynamic RAM (DRAM), floating-body RAM (FB-RAM), single-transistor cell memory.

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Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Cited by 20 publications

References 20 publications

Scaling of advanced floating body Z-RAM storage cells: A modeling approach

Scaling of advanced floating body Z-RAM storage cells: A modeling approach

Thorough Understanding of Retention Time of Z2FET Memory Operation

Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM

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