A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping is presented. Excellent electrostatic integrity and resulting tolerance to low channel doping are perceived as the main FinFET advantages, resulting in a dramatic reduction of statistical variability due to random discrete dopants (RDD). It is found that line edge roughness (LER), metal gate granularity (MGG) and interface trapped charges (ITC) dominate the parameter fluctuations with different distribution features, while RDD may result in relatively rare but significant changes in the device characteristics.
In this paper, we present models and tools developed and used by the Device Modelling Group at the University of Glasgow to study statistical variability introduced by the discreteness of charge and matter in contemporary and future Nano-CMOS transistors. The models and tools, based on Drift-Diffusion (DD), Monte Carlo (MC) and NonEquilibrium Green's Function (NEGF) techniques, are encapsulated in the Glasgow 3D statistical 'atomistic' device simulator. The simulator can handle most of the known sources of statistical variability including Random Discrete Dopants (RDD), Line Edge Roughness (LER), Thickness Fluctuations in the Oxide (OTF) and Body (BTF), granularity of the Poly-Silicon (PSG), Metal Gate (MGG) and High-κ (HKG), and oxide trapped charges (OTC). The results of the statistical simulations are verified with respect to measurements carried out on fabricated devices. Predictions about the magnitude of the statistical variability in future generations of nano-CMOS devices are also presented.
Abstract-The Z 2 -FET operation as capacitor-less DRAM is analyzed using advanced 2D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28 nm FD-SOI devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z 2 -FET's memory state is not exclusively defined by the inner charge but also by the reading conditions.
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