Extended Analysis of the $Z^{2}$ -FET: Operation as Capacitorless eDRAM

Abstract

Abstract-The Z 2 -FET operation as capacitor-less DRAM is analyzed using advanced 2D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28 nm FD-SOI devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z 2 -FET's memory state is not exclusively defined by the inner charge but also by the reading conditions.

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs

“…Included models and parameters are room temperature (300 K), SRH (Shockley-Read-Hall) recombination/generation, surface recombination, band-to-band tunneling (BtBT) and several mobility models (doping dependence, high field velocity saturation, transverse electric field with remote-Coulomb scattering, and thin-layer) [18]. Additional details regarding the Z 2 -FET architecture and simulation features can be found in [12].…”

“…Typical DC I A (V A ) switching characteristics were experimentally characterized from significantly wide devices. DC results were used to fit a 2D simulation deck [12], [17] from which the final 3D structure was built. Figure 1 illustrates, on the one hand, the characteristic Z 2 -FET sharp current onset at V A = V ON and, on the other hand, the curve fitting with the experimental results demonstrating an excellent agreement.…”

Experimental Demonstration of Operational Z2-FET Memory Matrix

“…Scaling the cell might also improve the current logic '1' level due to the reduction in the series resistance and the lateral electric field increment. Exhaustive Z 2 -FET details, operating as isolated memory cell, are found in [10], [12].…”

${Z}^{\textsf {2}}$ -FET as Capacitor-Less eDRAM Cell For High-Density Integration

“…In order to operate the device as a memory, the gate terminals are biased with V F G > 0 V and V BG < 0 V to induce a complementary energy barrier, i.e. a P-N junction, at the boundary between the gated and ungated sections of the body [4], [5]. As a result, the device ends up as a N + -P-N-P + structure emulating a Shockley diode [7] with three homo-junctions (J1-3), Fig.…”

“…1b) are forward biased, the barriers collapse and the conductance hugely increases; this is the '1'-state. On the other hand, if the carrier concentration is reduced, energy barriers grow as in the deep depletion regime for a MOS capacitor [8], and the injection when reading is not enough to reduce the barriers [4], [5]. The conductivity then remains low, '0'-state, Fig.…”