3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z²-FETs

Abstract

3D numerical TCAD simulations, based on experimental results, are performed to study the origin of the large Z 2-FET DRAM memory cell-to-cell variability on FD-SOI technology. The body width, cross-section shape and the passivation-induced lateral and top interface state density impacts on the device dynamic memory operation are investigated at room temperature. The width and body shape arise as marginal metrics not strongly inducing fluctuations in the device triggering conditions. However, the interface state (Dit) control, especially at the top of the ungated section, emerges as the main challenge since traps significantly increase the ON voltage variability threatening the capacitor-less DRAM operation.

Simulation studies on electrical characteristics of silicon nanowire feedback field-effect transistors with interface trap charges

“…Despite the advantages of the GAA SiNW structure, the downscaling of transistors raises significant problems during the device fabrication process. The influence of trap charges located within the interface has been reported by other research groups 7 – 14 . The interface trap charges (ITCs) induce device degradation with respect to the SS , on/off current ratio, and a shift in the threshold voltage ( V TH ).…”

Memory Operation of Z²-FET Without Selector at High Temperature

“…As more devices are included to the matrix, it is more likely to have a device with deviation from the average memory window which can impact the memory operation. However, previous study [20] report that the change on VON is no larger than 170 mV which the 230 mV window would be safe in most situations if the window is adequately centered.…”

A Review of Sharp-Switching Band-Modulation Devices

“…An excessive density of interface defects at the top of the ungated region degrades the capacitorless operation, increasing the V ON and the variability. This effect was found to be more critical as the cell was scaled down [47]. Nevertheless, a proper design strategy could alleviate the impact of high interface state densities in short cells and recover the sharp-switching capability at the expense of larger biasing voltages.…”

“…Nonetheless, the Z 2 -FET cell is comparable in terms of area per bit with advanced embedded DRAM that inherently includes a storage capacitor [48]. The geometric scaling enables enhanced oxide reliability, due to the dielectric surface reduction [44] but, as a drawback, it may degrade the retention time and the variability [47], demanding additional bias tuning to overcome this issue.…”