As CMOS scales down, hot carrier aging (HCA) scales up and can be a limiting aging process again. This has motivated re-visiting HCA, but recent works have focused on accelerated HCA by raising stress biases and there is little information on HCA under use-biases. Early works proposed that HCA mechanism under high and low biases are different, questioning if the high-bias data can be used for predicting HCA under use-bias. A key advance of this work is proposing a new methodology for evaluating the HCA-induced variation under use-bias. For the first time, the capability of predicting HCA under use-bias is experimentally verified. The importance of separating RTN from HCA is demonstrated. We point out the HCA measured by the commercial SourceMeasure-Unit (SMU) gives erroneous power exponent. The proposed methodology minimizes the number of tests and the model requires only 3 fitting parameters, making it readily implementable.
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Variability of nanometer-size devices is a major challenge for circuit design. Apart from the as-fabricated variability, the postfabrication degradation introduces a timedependent variability, originating from statistical distribution of charge location and number. The existing characterization techniques do not always capture the maximum degradation. Some of them does not separate the device-to-device variation from the charging fluctuation within the same device, either. The objective of this paper is to develop a new analysis method for characterizing time-dependent device-to-device variation, accounting for within-device fluctuation (TVF). The TVF captures the maximum degradation, separate device-to-device variation from withindevice fluctuation, and reduce the data points by three orders of magnitude. It is shown that the popular data acquisition at discrete time points does not capture the fluctuation well and drain current must be measured continuously. The TVF shows that degradation has two components-a fluctuation with time and one whose discharge is not observed under a given bias. Although both of them increase with stress time, the correlation between them is weak, indicating two different origins.
Abstract-The Z 2 -FET operation as capacitor-less DRAM is analyzed using advanced 2D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28 nm FD-SOI devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z 2 -FET's memory state is not exclusively defined by the inner charge but also by the reading conditions.
The band-modulation and sharp-switching mechanisms in Z 2 -FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z 2 -FET is suitable for embedded memory applications.
SRAM is vulnerable to device-to-device variation (DDV), since it uses minimum-sized devices and requires device matching. In addition to the as-fabricated DDV at time-zero, aging induces a time-dependent DDV (TDDV). Bias temperature instability (BTI) is a dominant aging process. A number of techniques have been developed to characterize the BTI, including the conventional pulse-I-V , random telegraph noises, time-dependent defect spectroscopy, and TDDV accounting for the within-device fluctuation. These techniques, however, cannot be directly applied to SRAM, because their test conditions do not comply with typical SRAM operation. The central objective of this paper is to develop a technique suitable for characterizing both the negative BTI (NBTI) and positive BTI (PBTI) in SRAM. The key issues addressed include the SRAM relevant sensing Vg, measurement delay, capturing the upper envelope of degradation, sampling rate, and measurement time window. The differences between NBTI and PBTI are highlighted. The impact of NBTI and PBTI on the cell-level performance is assessed by simulation, based on experimental results obtained from individual devices. The simulation results show that, for a given static noise margin, test conditions have a significant effect on the minimum operation bias.
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