Thorough Understanding of Retention Time of Z2FET Memory Operation

Duan, Meng; Navarro, C.; Cheng, Binjie; Adamu-Lema, Fikru; Wang, Xingsheng; Georgiev, Vihar P.; Gamiz, F.; Millar, C.; Asenov, A.

doi:10.1109/ted.2018.2877977

Cited by 12 publications

(11 citation statements)

References 17 publications

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“…More important is that interface states are strongly related, via the trap capture cross-section (σ) dependence with the trap energy [22], with the wide retention time variability observed in capacitorless cells [23], [24]. Since retention time in long Z 2 -FETs is driven by the SRH generation at the anode-body junction [4], reducing the surface recombination velocity negatively impacts this figure of merit. On the other hand, faster recombination rates slightly enhance the retention time.…”

Section: B Retention Timementioning

confidence: 99%

“…The Z 2 -FET device [1], [2] is gaining momentum nowadays [3]. This double gated SOI (Silicon-on-Insulator) p-i-n diode is currently being extensively investigated via advanced TCAD simulations [4], [5] and through experiments [6], [7], as a possible DRAM replacement for embedded memory applications. As other single-transistor cells [8], [9], the Z 2 -FET main advantage favoring its adoption is the possibility of getting rid of the external capacitor.…”

Section: Z 2 -Fet Introduction and Basicsmentioning

confidence: 99%

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3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z²-FETs

Navarro

Vilanova

Márquez

et al. 2019

IEEE Trans. Electron Devices

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3D numerical TCAD simulations, based on experimental results, are performed to study the origin of the large Z 2-FET DRAM memory cell-to-cell variability on FD-SOI technology. The body width, cross-section shape and the passivation-induced lateral and top interface state density impacts on the device dynamic memory operation are investigated at room temperature. The width and body shape arise as marginal metrics not strongly inducing fluctuations in the device triggering conditions. However, the interface state (Dit) control, especially at the top of the ungated section, emerges as the main challenge since traps significantly increase the ON voltage variability threatening the capacitor-less DRAM operation.

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Section: B Retention Timementioning

confidence: 99%

Section: Z 2 -Fet Introduction and Basicsmentioning

confidence: 99%

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z²-FETs

Navarro

Vilanova

Márquez

et al. 2019

IEEE Trans. Electron Devices

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“…5. The Shockley-Read-Hall (SRH) generation explains that carrier density of electron and hole may be increased with the temperature in the channel body, which causes the reduction of potential barrier [18]. Consequently, the reliable memory operation depends on whether the potential barrier prevents the carrier injection into the channel body and the '0'-state is sustained or not.…”

Section: Memory Operationmentioning

confidence: 99%

“…The main purpose of this work is to experimentally investigate the reliability of Z 2 -FET device and matrix memory at wider temperature range from 25 °C to 175 °C through DC and transient characteristics. Also, the failure mechanism of memory operation has been studied through experimental and simulation results unlike previous studies [15], [18], [19]. Lastly, matrix operation without using selector has been successfully demonstrated in elevated temperature for the first time to confirm the reliable matrix memory operation.…”

Section: Introductionmentioning

confidence: 97%

Memory Operation of Z²-FET Without Selector at High Temperature

Kwon

Navarro

Gamiz

et al. 2021

IEEE J. Electron Devices Soc.

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The electrical performance of Z 2 -FET and memory operations of matrix are demonstrated at high temperatures up to 125 °C. The sharp subthreshold slope is maintained and the reliable operation is ensured within the memory window of 229 mV even though the turn on voltage of '0'-and '1'-states are shifted to lower voltage. The '0'-state current remains low while the '1'-state current gradually increases as the temperature increases leading to higher current margin. At the elevated temperature, the potential barriers are slightly reduced but does not collapse, which leads to the successful memory operation. However, increasing the temperature over 125 °C, the potential barrier at the '0'-state is significantly reduced and causes the failure of memory operation with high '0'-state current. The matrix demonstrates reliable memory operations without using selector circuits even at 125 °C.

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“…The accumulation may originate from the Shockley-Read-Hall (SRH)-induced generation or band-to-band tunneling (BTBT) generation. [21] Nevertheless, a unique feature of our device, which is the gate voltage of 0 V under the read condition, prevents read "0" failure from SRH generation. Moreover, the use of lightly doped drain extensions reduces the BTBT generation rate, thereby maintaining state "0."…”

Section: Introductionmentioning

confidence: 99%

Quasi‐Nonvolatile Silicon Memory Device

Lim

Son

Cho

2020

Adv Materials Technologies

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Several attempts have been made to store charges in the channel regions of silicon transistors, such as in zero-capacitor random-access memories (Z-RAMs), [7,8] metastable DRAMs (MSDRAMs), [9,10] advanced RAMs (A-RAMs), [11,12] and zeroslope and zero-impact ionization RAMs (Z 2-RAMs). [13,14] Among these, Z 2-RAMs are capable of low-voltage operation with high speed, long retention time, and nondestructive reading capability, because of the positive feedback loop. [15] However, electrostatic doping induced by gate bias is required to form a potential well, which is important for the positive feedback loop. [16,17] Although thyristor RAMs (T-RAMs) employ doping regions to form the potential well, external bias is still necessary for TRAMs to retain the stored charges. [18-20] This indispensable bias for holding the stored charges has restricted their use in quasi-nonvolatile memory applications. In this paper, we propose a fully CMOS-compatible p +-n-pn + silicon memory device to enable quasi-nonvolatile memory functionality with high speed, long retention time, and nondestructive reading capability. Using a well-defined potential well in a p +-n-p-n + silicon structure with a gated n-channel region, our device utilizes holes as majority charge carriers for the positive feedback loop, unlike TRAMs which use electrons as majority charge carriers. Hence, our quasi-nonvolatile silicon memory device can retain the charges stored in the channel region without requiring any external bias, for a long time. In addition, the positive-feedback loop enables low-voltage operation, high speed, and nondestructive reading for quasi-nonvolatile memory applications. 2. Results and Discussion A quasi-nonvolatile silicon memory device consists of p +-n-p-n + regions on a silicon-on-insulator (SOI) substrate (Figure 1a). An SiO 2 /poly-Si gate stack is located on the upper side of the n-channel region. The poly-Si gate modulates the potential barrier of the n-channel region; it controls the hole injection from the p + drain region. The p-channel region is designated to block the electron injection from the n + source region. The channel regions also form potential wells; states "1" and "0" are defined by presence and absence of excess charge carriers in the potential wells, respectively. The corresponding energy band diagrams exhibit the difference in the channel region between the two states (Figure 1b). Barrier-height modulation by carrier accumulation in the potential wells is essential for the positive feedback loop, which allows memory operations. Memory hierarchy among conventional memory technologies is one of the main bottlenecks in modern computer systems; alternative memory technologies are thus necessary for quasi-nonvolatile memory applications. Herein, a fully complementary metal-oxide-semiconductor-compatible quasi-nonvolatile memory composed of p +-n-p-n + silicon on a silicon-on-insulator substrate is presented. The quasi-nonvolatile silicon memory device demonstrates highspeed write capability (≤100 ns), long retenti...

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Thorough Understanding of Retention Time of Z2FET Memory Operation

Cited by 12 publications

References 17 publications

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z²-FETs

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z²-FETs

Memory Operation of Z²-FET Without Selector at High Temperature

Quasi‐Nonvolatile Silicon Memory Device

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Thorough Understanding of Retention Time of Z2FET Memory Operation

Cited by 12 publications

References 17 publications

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs

Memory Operation of Z²-FET Without Selector at High Temperature

Quasi‐Nonvolatile Silicon Memory Device

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3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z²-FETs

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z²-FETs