Quasi‐Nonvolatile Silicon Memory Device

Abstract

Several attempts have been made to store charges in the channel regions of silicon transistors, such as in zero-capacitor random-access memories (Z-RAMs), [7,8] metastable DRAMs (MSDRAMs), [9,10] advanced RAMs (A-RAMs), [11,12] and zeroslope and zero-impact ionization RAMs (Z 2-RAMs). [13,14] Among these, Z 2-RAMs are capable of low-voltage operation with high speed, long retention time, and nondestructive reading capability, because of the positive feedback loop. [15] However, electrostatic doping induced by gate bias is required to form a potential well, which is important for the positive feedback loop. [16,17] Although thyristor RAMs (T-RAMs) employ doping regions to form the potential well, external bias is still necessary for TRAMs to retain the stored charges. [18-20] This indispensable bias for holding the stored charges has restricted their use in quasi-nonvolatile memory applications. In this paper, we propose a fully CMOS-compatible p +-n-pn + silicon memory device to enable quasi-nonvolatile memory functionality with high speed, long retention time, and nondestructive reading capability. Using a well-defined potential well in a p +-n-p-n + silicon structure with a gated n-channel region, our device utilizes holes as majority charge carriers for the positive feedback loop, unlike TRAMs which use electrons as majority charge carriers. Hence, our quasi-nonvolatile silicon memory device can retain the charges stored in the channel region without requiring any external bias, for a long time. In addition, the positive-feedback loop enables low-voltage operation, high speed, and nondestructive reading for quasi-nonvolatile memory applications. 2. Results and Discussion A quasi-nonvolatile silicon memory device consists of p +-n-p-n + regions on a silicon-on-insulator (SOI) substrate (Figure 1a). An SiO 2 /poly-Si gate stack is located on the upper side of the n-channel region. The poly-Si gate modulates the potential barrier of the n-channel region; it controls the hole injection from the p + drain region. The p-channel region is designated to block the electron injection from the n + source region. The channel regions also form potential wells; states "1" and "0" are defined by presence and absence of excess charge carriers in the potential wells, respectively. The corresponding energy band diagrams exhibit the difference in the channel region between the two states (Figure 1b). Barrier-height modulation by carrier accumulation in the potential wells is essential for the positive feedback loop, which allows memory operations. Memory hierarchy among conventional memory technologies is one of the main bottlenecks in modern computer systems; alternative memory technologies are thus necessary for quasi-nonvolatile memory applications. Herein, a fully complementary metal-oxide-semiconductor-compatible quasi-nonvolatile memory composed of p +-n-p-n + silicon on a silicon-on-insulator substrate is presented. The quasi-nonvolatile silicon memory device demonstrates highspeed write capability (≤100 ns), long retenti...

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors

“…Thus, the p -FBFET (or n -FBFET) changes to an on-state under a V GS of − 1 V (or 1 V). During hold operation under no-bias conditions, the accumulated charge carriers in the potential wells are maintained until the potential barriers in the channels are well-defined, and the FBFETs have quasi-nonvolatile memory characteristics 38 , 39 . In the V GS positive (or negative) sweep for the p -FBFET (or n -FBFET), the charge carriers accumulated in the channel regions are reduced, and the two potential barriers are regenerated.…”

An Ultrafast Nonvolatile Memory with Low Operation Voltage for High‐Speed and Low‐Power Applications

“…Its long retention time (over 10 4 s) is 1.5 × 10 5 times and 100 times longer than that of DRAMs and the reported quasi‐nonvolatile memories, respectively. [ 3,14–16 ] The ultrahigh operation speed (8 ns) of our memory is ≈10 4 times and 10 6 times faster than that of the commercial NAND/NOR flash memories and the nonvolatile memories based on 2D materials, respectively. [ 5,23,43,44 ] Given the retention time of the device (10 4 s) is still far from the requirement of memory applications, in which more than 10 years’ retention is favorable, one of the potential applications of the memory device is RAMs.…”

“…[ 1,3,5 ] To break the limitation of “memory wall,” great efforts have been paid to develop ultrafast nonvolatile memory with ultrahigh operation speed, long‐term retention, and low power consumption. [ 6–13 ] For instance, quasi‐nonvolatile memories based on a semi‐floating‐gate architecture were proposed recently, [ 3,14–16 ] which can fill the timescale gap between volatile and nonvolatile memories. However, the retention time of these quasi‐nonvolatile memories are still limited (<100 s), and a relatively high gate voltage is required.…”

Highly Reliable Memory Operation of High Density Three-Terminal Thyristor Random Access Memory

“…To reliably simulate the Si-based 3-T TRAM, the physics models of the simulation are adjusted by using the experimental data of I A -V AC characteristics for various V GC s in the p + -n-p-n + silicon memory device with a gated base (Fig. 2) [20]. Speci cally, the parameters of the recombination model are adjusted and the Si-SiO 2 surface SRH recombination model is adopted to re ect the data retention characteristics of real devices affected by junction and interface defects.…”