In this study, a high-performance AlGaN/GaN high electron mobility transistor (HEMT) is presented to improve its electrical operation by employing an inner field-plate (IFP) structure. Prior to the IFP structure analysis, we compared the measured and simulated direct current characteristics of the fabricated two-finger conventional T-shaped gate HEMTs. Then, the AlGaN/GaN HEMT with a drain-side field plate (FP) structure was suggested to enhance the breakdown voltage characteristics. The maximum breakdown voltage recorded with a 0.8 µm stretched FP structure was 669 V. Finally, the IFP structure was interfaced with the gate head of the device to compensate the radio frequency characteristics, choosing the optimum length of the drain-side FP structure. Compared to the 0.8 µm stretched FP structure, the IFP structure showed improved frequency characteristics with minimal difference to the breakdown voltage. The frequency variation caused by changing the passivation thickness was also analyzed, and the optimum thickness was identified. Thus, IFP AlGaN/GaN HEMT is a promising candidate for high-power and high-frequency applications.
In this study, we consider the relationship between the temperature in a two-dimensional electron gas (2-DEG) channel layer and the RF characteristics of an AlGaN/GaN high-electron-mobility transistor by changing the geometrical structure of the field-plate. The final goal is to achieve a high power efficiency by decreasing the channel layer temperature. First, simulations were performed to compare and contrast the experimental data of a conventional T-gate head structure. Then, a source-bridged field-plate (SBFP) structure was used to obtain the lower junction temperature in the 2-DEG channel layer. The peak electric field intensity was reduced, and a decrease in channel temperature resulted in an increase in electron mobility. Furthermore, the gate-to-source capacitance was increased by the SBFP structure. However, under the large current flow condition, the SBFP structure had a lower maximum temperature than the basic T-gate head structure, which improved the device electron mobility. Eventually, an optimum position of the SBFP was used, which led to higher frequency responses and improved the breakdown voltages. Hence, the optimized SBFP structure can be a promising candidate for high-power RF devices.
Three-terminal (3-T) thyristor random-access memory is explored for a next-generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate–cathode voltage (VGC,ST) and anode–cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of − 0.4 V and VAC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate–cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.
Three-terminal (3-T) thyristor random-access memory is explored for a next generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate-cathode voltage (VGC,ST) and anode- cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of -0.4 V and VAC,ST of 0.55 V shows the continuous data retention capability without refresh operation with a low standby current of 0.13 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on the adjacent unselected cells by adjusting gate-cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.
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