Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory

Abstract

Three-terminal (3-T) thyristor random-access memory is explored for a next-generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate–cathode voltage (VGC,ST) and anode–cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of − 0.4 V and VAC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate–cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.

Schottky Barrier Memory based on Heterojunction Bandgap Engineering for High-density and Low-power Retention

“…In addition, this limitation imposes constraints on the maximum attainable array size 17 . The TRAM has the advantage of maintaining data with low standby power through a holding voltage without the need for the refresh operation 11,12 .…”

“…In order to overcome these limitations, extensive research has been conducted on silicon-based highdensity memories due to their high compatibility with conventional Si CMOS processes and high-speed operations [8][9][10][11][12] . Among them, bistable resistor (biristor) and thyristor RAM (TRAM) have received much attention, with many studies being focused on their primary memory mechanisms [13][14][15][16] .…”

“…However, a notable concern arises from the steep current slope near the region where the holding voltage is determined [11][12] . In the memory array con gurations, a consistently low standby current is essential over a wide voltage range, considering device variations and operating voltage margins.…”