In this paper, we propose inverting logic-in-memory (LIM) cells comprising silicon nanowire feedback field-effect transistors with steep switching and holding characteristics. The timing diagrams of the proposed inverting LIM cells under dynamic and static conditions are investigated via mixed-mode technology computer-aided design simulation to verify the performance. The inverting LIM cells have an operating speed of the order of nanoseconds, an ultra-high voltage gain, and a longer retention time than that of conventional dynamic random access memory. The disturbance characteristics of half-selected cells within an inverting LIM array confirm the appropriate functioning of the random access memory array.

The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations. Here, we present a NAND and NOR LIM composed of silicon nanowire feedback field-effect transistors, whose configuration resembles that of CMOS logic gate circuits. The LIM can perform memory operations to retain its output logic under zero-bias conditions as well as logic operations with a high processing speed of nanoseconds. The newly proposed dynamic voltage-transfer characteristics verify the operating principle of the LIM. This study demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues.

In this study, we propose an inverter consisting of reconfigurable double-gated (DG) feedback field-effect transistors (FBFETs) and examine its logic and memory operations through a mixed-mode technology computer-aided design simulation. The DG FBFETs can be reconfigured to n- or p-channel modes, and these modes exhibit an on/off current ratio of ~ 1012 and a subthreshold swing (SS) of ~ 0.4 mV/dec. Our study suggests the solution to the output voltage loss, a common problem in FBFET-based inverters; the proposed inverter exhibits the same output logic voltage as the supply voltage in gigahertz frequencies by applying a reset operation between the logic operations. The inverter retains the output logic ‘1’ and ‘0’ states for ~ 21 s without the supply voltage. The proposed inverter demonstrates the promising potential for logic-in-memory application.

In this study, the temperature-dependent electrical characteristics of p-channel mode feedback field-effect transistors (FBFETs) were examined at temperatures ranging from 250 to 425 K. Their steep subthreshold swings of less than 1 mV/dec were maintained even at temperatures up to 400 K. As the temperature increased to 400 K, the latch-up voltage shifted from −0.951 to −0.613 V, which was caused by a reduction in the potential barriers in the channels of the FBFETs. High Ion/Ioff ratios above 108 were maintained in the temperature range of 250 to 400 K. However, at temperatures over 400 K, the FBFETs were turned on regardless of the gate voltages owing to the generation of a thermally induced positive feedback loop.INDEX TERMS Field-effect transistor, positive feedback loop, temperature-dependent, simulation.

The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations. Here, we present a NAND and NOR LIM composed of silicon nanowidre feedback field-effect transistors, whose configuration resembles that of CMOS logic gate circuits. The LIM can perform memory operations to retain its output logic under zero-bias conditions as well as logic operations with a high processing speed of nanoseconds. The newly proposed dynamic voltage-transfer characteristics verify the operating principle of the LIM. This study demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues.

In this paper, we propose the design optimization of underlapped Si1–xGex-source tunneling field-effect transistors (TFETs) with a gate-all-around structure. The band-to-band tunneling rates, tunneling barrier widths, I–V transfer characteristics, threshold voltages, on/off current ratios, and subthreshold swings (SSs) were analyzed by varying the Ge mole fraction of the Si1–xGex source using a commercial device simulator. In particular, a Si0.2Ge0.8-source TFET among our proposed TFETs exhibits an on/off current ratio of approximately 1013, and SS of 27.4 mV/dec.

The reconfigurable feedback field‐effect transistors (R‐FBFETs) with a double‐gated structure are designed and the logic and memory operations of a logic‐in‐memory (LIM) inverter comprising two R‐FBFETs are investigated. The R‐FBFETs exhibit an extremely low subthreshold swing of ≈1 mV dec−1, a high on/off current ratio of ≈107, and a long retention time of 10 s, owing to a positive feedback loop mechanism. The on‐current ratio of the p‐ to n‐channel modes is 1.03, which indicates a high degree of reconfigurability. The LIM inverter retains the output logic “1” and “0” states for over 50 s under zero‐bias conditions. The symmetric reconfigurable switching and memory operations of the R‐FBFETs enable the LIM inverter to perform logic and memory operations for a long retention time without a power supply.

In this study, the device characteristics of silicon nanowire feedback field-effect transistors were predicted using technology computer-aided design (TCAD)-augmented machine learning (TCAD-ML). The full current–voltage (I-V) curves in forward and reverse voltage sweeps were predicted well, with high R-squared values of 0.9938 and 0.9953, respectively, by using random forest regression. Moreover, the TCAD-ML model provided high prediction accuracy not only for the full I-V curves but also for the important device features, such as the latch-up and latch-down voltages, saturation drain current, and memory window. Therefore, this study demonstrated that the TCAD-ML model can substantially reduce the computational time for device development compared with conventional simulation methods.