Design of a 128-Mb SOI DRAM Using the Floating Body Cell (FBC)

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

“…Some kinds of capacitor-less DRAM cell have been proposed and developed [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. Floating body cell (FBC) is a promising candidate in view of its simple structure and scalability.…”

1T-capacitorless bulk memory: Scalability and signal impact

“…With standard retention polarization [2,4,5], source and drain bias to 0V, the drain and source junctions are forward biased when a "1" state is set. It results in quick signal loss for "1" state.…”

“…It results in injection of electrons in memory floating body. To avoid it, a possible way is to add local wordlines (WL) [5]. But, this solution increases significantly silicon area due to needed additional WL switch.…”

“…The reference may consist of multiple reference cells generating a mean current value that reduces the dispersion of the reference [2,5] .To guarantee a correct read of the bitcell state, it is necessary that the reference cell current to be greater than the current of all memory cells programmed to "0", and less than the one of all memory cells programmed to "1". Fig.…”

Advanced memory concepts for DRAM and nonvolatile memories

“…Because the cell is composed of one transistor, FBC has simple and compact structure. In this case, back gate is used for the charge accumulation in the body [8][9][10]. This structure is the modified double gate configuration.…”