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The memory cell characteristics of the FBC (Floating Body Cell) have been experimentally verified by 0.175pm cell may for the fin1 time. The FBC is a oneffansistar gain cell, which is a suitable s " c N r e for the future embedded DRAM an SO1 wafer. The memory cell layout and the pmcess integration have been designed t o m the viewpoint of the logic process compatibility withont sacrificing the data retention characteristics. The salicide pmess with the polySi plug is implemented into the process integration. The most important device characteristics for realizing the FBC is the threshold voltage difference ( AVth) of the cell transistor between "1" state and "0" state. The key device parameten in order to enlarge the A Vth are experimentally clarified. A AVth of 0.4V has been obtained, which leads to 99.77% function bit yield of 96Kbit ADM (Array Diagnostic Monitor). The retention time of 5sec has been realized at the r w m temperarure.

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