A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

“…The second one is large retention time of ''0" hold. The same as for the conventional DRAM cell, the retention time can be controlled by the electrical field of pn junction [15,18]. In the case of FBC, we have suppressed the electrical field almost 0.7 MV/cm.…”

“…Some kinds of capacitor-less DRAM cell have been proposed and developed [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. Floating body cell (FBC) is a promising candidate in view of its simple structure and scalability.…”

Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs

“…The ''$" symbol in some fields means that the information is not available. I on /I off = 20 T Ret > 1 s @ 25°C Toshiba [4] Impact ionization FDSOI (90 nm/$/55 nm/25 nm) SM = 50 lA/lm T Ret = 100 ms @ 85°C Intel [5] Impact ionization UTB FDSOI (55 nm/65 nm/25 nm/10 nm) SM = 3 lA/lm $ Samsung [6] Bipolar junction transistor PDSOI (55 nm/100 nm/$/$) I ON /I OFF = 10 4 À10 6 T Ret = 8 ms @ 85°C Innovative silicon [7] Bipolar junction transistor FinFET/trigate (110 nm/60 nm/100 nm/$) S M = 1 5 lA/Fin $ The impact of the device size and front/back gate biases has been investigated systematically. The transistors under test were not optimized for memory applications.…”

“…Indeed, the SOI transistors floating body can be used to store charges [1]. This property has led to an increasing number of single-transistor SOI DRAM (1T-DRAM) concepts [1][2][3][4][5][6][7][8][9]. In all those variants, the 'ON' state (bit '1') reflects the presence of excess majority carriers in the body which increases its potential and the drain current.…”

“…In the approach reported by Toshiba, the 'ON' state programming is achieved by impact ionization [4]. This technology is based on Fully Depleted SOI transistors (FDSOI) where the back gate is negatively biased to store the hole charge and adjust the threshold voltage.…”