FBC (Floating Body Cell) for embedded DRAM on SOI

Inoh, K.; Shino, T.; Yamada, Hisao; Nakajima, H.; Minami, Y.; Yamada, Takashi; Ohsawa, Takashi; Higashi, Taneaki; Fujita, Katsushi; Ikehashi, Tamio; Kajiyama, Tisato; Fukuzumi, Y.; Hamamoto, T.; Ishiuchi, H.

doi:10.1109/vlsit.2003.1221087

Cited by 36 publications

(10 citation statements)

References 2 publications

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“…Some kinds of capacitor-less DRAM cell have been proposed and developed [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. Floating body cell (FBC) is a promising candidate in view of its simple structure and scalability.…”

Section: Introductionmentioning

confidence: 99%

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Hamamoto

Ohsawa

2009

Solid-State Electronics

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Section: Introductionmentioning

confidence: 99%

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Hamamoto

Ohsawa

2009

Solid-State Electronics

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“…The peak is obtained at 326.72 nm (∼3.79 eV) while a trailing defect emission starting from 400 nm represents the surface defects which leads to the charge trapping sites on the surface of TiO 2 film [8]. Since the electron tunneling across the Al 2 O 3 layer occurs at low voltage, the kink effect in the transistor characteristics obtained by using a TiO 2 layer as floating body can be explored for designing the low power memory devices with further scaling at industrial grade [6]. This phenomenon can reduce the voltage of read/write operation thereby improving the efficiency of the memory devices.…”

Section: Resultsmentioning

confidence: 99%

“…The charge trapping in the ATA structure is largely responsible for this effect. The kink effect has both its advantage and disadvantage over the memory devices: DRAM loses information from the memory cells due to off‐state leakages induced by the kink [5], while the ZRAM and TRAM use this phenomenon for charge storage [6]. This Letter presents the study of the occurrence of kink effect in TiO 2 embedded ZnO QDs‐based TFT at a voltage of ∼1.15 V. As per best of our knowledge, no such kind of results is reported for the ZnO QDs‐based TFT using TiO 2 as a floating gate.…”

Section: Introductionmentioning

confidence: 99%

Kink effect in TiO ₂ embedded ZnO quantum dot‐based thin film transistors

Kumar¹,

Kumar²,

Singh³

et al. 2017

Electron. lett.

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The kink effect at a very low voltage (∼1.15 V) region is reported in the electrical characteristics of a back-gated thin film transistor fabricated by embedding a TiO 2 (T) layer between two Al 2 O 3 (A) layers grown on a p-Si substrate using electron beam evaporation. A layer of ZnO quantum dots (QDs) deposited on the AT A structure by the sol-gel method is used for charge transportation between the source and drain electrodes grown on the ZnO QDs layer. The effect of TiO 2 is analysed for the charge trapping and possible occurrence of the kink effect.

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“…Capacitor-less one transistor DRAM cells are an important development which takes advantage of the floating body effect in SOI devices [25,26]. The generation of excess negative or positive charge in the body can be used to store data states.…”

Section: Capacitor Less Dramsmentioning

confidence: 99%

Embedding Device Solutions in Engineered Substrates

Mazuré¹

2007

ECS Trans.

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A review of the advances in Smart Cut engineered substrates and the impact on device architecture and IC design is given. Primarily focusing on CMOS applications, mobility enhancing substrates, fully depleted device compatibility to SOI product capability and multi-gate FinFETs will be reviewed. IntroductionA simple structure like silicon on insulator (SOI) has allowed the IC industry to optimize the MOSFET architecture by reducing parasitic capacitances to the substrate, cutting device leakage, improving device speed while reducing power consumption, decreasing considerably soft error rate, and so forth. The benefits and potential of SOI have been known since the 60's [1]. The real issue for an industrial SOI development was SOI substrate availability and wafer quality. This roadblock vanished with the invention of Smart Cut TM [2,3], a single crystal thin layer transfer technology. The simplicity of this technique underlines simultaneously the power and potential of Smart Cut technology and explains why it has become today the industrial standard for thin layer transfer [4].Smart Cut technology consists in defining a splitting region within the donor substrate by ion implantation (e.g. H), which allows a thin film to transfer to a handle wafer after bonding and splitting. The thickness removed from the donor wafer is negligible compared to the total wafer thickness. Consequently, the donor wafer can be reused many times. A range of 10 nm up to a few 10 3 nm in top Si and buried oxide (BOX) thickness is easily covered by this technology.Beyond SOI, Smart Cut technology opens the door to substrate engineering, i.e. the capability to design new substrates tailored to specific applications [5]. It is possible to amplify certain device properties while weakening others by combining different materials or crystal orientations, adding strained layers, or simply creating a new composite substrate.High performance ICs continue to be the driver for a specialized family of advanced substrates. Ultra-thin (UT) SOI, mobility enhancing substrates like strained SOI (sSOI) in addition to local strain techniques [6], as well as improved thermal dissipation to reduce the impact of hot spots on MOSFET performance are among the most obvious engineered substrate solutions [5]. Direct silicon Bonding (DSB) adds a high-end mobility enhancing substrate to the bulk Si IC architectures [7]. Non-planar device architectures like FinFETs take advantage of the buried oxide or nitride as an etch stop for fin height definition, thus reducing fin variability [5].A review of the advances in Smart Cut engineered substrates and the impact on device performance and IC design is given below. High Performance SubstratesBeyond the 90nm technology node, the electron and hole mobility enhancement have become essential to assure device performance increase while scaling. Two approaches are clearly identified: strained silicon, and dual crystal orientation surfaces. The first one is evolutionary and takes advantage of strain inducing CMOS processes whi...

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FBC (Floating Body Cell) for embedded DRAM on SOI

Cited by 36 publications

References 2 publications

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Kink effect in TiO ₂ embedded ZnO quantum dot‐based thin film transistors

Embedding Device Solutions in Engineered Substrates

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FBC (Floating Body Cell) for embedded DRAM on SOI

Cited by 36 publications

References 2 publications

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Kink effect in TiO 2 embedded ZnO quantum dot‐based thin film transistors

Embedding Device Solutions in Engineered Substrates

Contact Info

Product

Resources

About

Kink effect in TiO ₂ embedded ZnO quantum dot‐based thin film transistors