A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

Minami, Y.; Shino, T.; Sakamoto, Atsushi; Higashi, Taneaki; Kusunoki, N.; Fujita, Katsushi; Hatsuda, K.; Ohsawa, Takashi; Aoki, Naofumi; Tanimoto, Hiroshi; Morikado, M.; Nakajima, H.; Inoh, K.; Hamamoto, T.; Nitayama, A.

doi:10.1109/iedm.2005.1609336

Cited by 6 publications

(5 citation statements)

References 5 publications

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“…Co salicide and Cu wirings (6layers) were used to reduce parasitic resistance. Compared with the previous work [2], a new process has been adopted for locally reducing the thickness of SOI film in the cell array. Several new steps are performed before the STI formation.…”

Section: Fabrication and Characterizationmentioning

confidence: 99%

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Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Shino

Kusunoki

Higashi

et al. 2006

2006 International Electron Devices Meeting

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Section: Fabrication and Characterizationmentioning

confidence: 99%

“…In addition to device geometry, operation voltages should be carefully reduced in the scaling. In this paper, the latest data of the Floating Body RAM (FBRAM) [1,2] are demonstrated. A high chip yield has been obtained by reducing SOI thickness to 43nm.…”

Section: Introductionmentioning

confidence: 99%

Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Shino

Kusunoki

Higashi

et al. 2006

2006 International Electron Devices Meeting

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“…The development of the FBC technology is being attentively followed by the IC community. Recently a 128Mb FBC was reported [27] and its scalability to 32nm has been proven [28]. Further, the FBC concept has been proven to work as well for FinFET architecture [29].…”

Section: Capacitor Less Dramsmentioning

confidence: 99%

Embedding Device Solutions in Engineered Substrates

Mazuré¹

2007

ECS Trans.

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A review of the advances in Smart Cut engineered substrates and the impact on device architecture and IC design is given. Primarily focusing on CMOS applications, mobility enhancing substrates, fully depleted device compatibility to SOI product capability and multi-gate FinFETs will be reviewed. IntroductionA simple structure like silicon on insulator (SOI) has allowed the IC industry to optimize the MOSFET architecture by reducing parasitic capacitances to the substrate, cutting device leakage, improving device speed while reducing power consumption, decreasing considerably soft error rate, and so forth. The benefits and potential of SOI have been known since the 60's [1]. The real issue for an industrial SOI development was SOI substrate availability and wafer quality. This roadblock vanished with the invention of Smart Cut TM [2,3], a single crystal thin layer transfer technology. The simplicity of this technique underlines simultaneously the power and potential of Smart Cut technology and explains why it has become today the industrial standard for thin layer transfer [4].Smart Cut technology consists in defining a splitting region within the donor substrate by ion implantation (e.g. H), which allows a thin film to transfer to a handle wafer after bonding and splitting. The thickness removed from the donor wafer is negligible compared to the total wafer thickness. Consequently, the donor wafer can be reused many times. A range of 10 nm up to a few 10 3 nm in top Si and buried oxide (BOX) thickness is easily covered by this technology.Beyond SOI, Smart Cut technology opens the door to substrate engineering, i.e. the capability to design new substrates tailored to specific applications [5]. It is possible to amplify certain device properties while weakening others by combining different materials or crystal orientations, adding strained layers, or simply creating a new composite substrate.High performance ICs continue to be the driver for a specialized family of advanced substrates. Ultra-thin (UT) SOI, mobility enhancing substrates like strained SOI (sSOI) in addition to local strain techniques [6], as well as improved thermal dissipation to reduce the impact of hot spots on MOSFET performance are among the most obvious engineered substrate solutions [5]. Direct silicon Bonding (DSB) adds a high-end mobility enhancing substrate to the bulk Si IC architectures [7]. Non-planar device architectures like FinFETs take advantage of the buried oxide or nitride as an etch stop for fin height definition, thus reducing fin variability [5].A review of the advances in Smart Cut engineered substrates and the impact on device performance and IC design is given below. High Performance SubstratesBeyond the 90nm technology node, the electron and hole mobility enhancement have become essential to assure device performance increase while scaling. Two approaches are clearly identified: strained silicon, and dual crystal orientation surfaces. The first one is evolutionary and takes advantage of strain inducing CMOS processes whi...

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“…In this paper, several extension-less strategies for scaled UTBB and FinFET devices are evaluated for improved performance, shortchannel-effects (SCE), and variability control. Increased interest in potential memory architecture alternatives to the dynamic random-access memory (DRAM), such as the onetransistor floating body RAM (1T-FBRAM), [26][27][28][29][30][31] will also be addressed in this work through the use of a process flow fully compatible with UTBB logic technology.…”

Section: Introductionmentioning

confidence: 99%

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

Veloso¹,

Keersgieter²,

Aoulaiche³

et al. 2013

Jpn. J. Appl. Phys.

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In this work we explore the use of extension-less doping schemes for fully-depleted devices [two-dimensional (2D): ultra-thin body and buried-oxide layer (BOX) planar devices (UTBB); three-dimensional (3D): multi-gate field-effect transistor devices with the conduction channels wrapped around silicon (Si) fins (FinFETs) and built on bulk-Si or silicon-on-insulator (SOI) substrates], suitable for advanced logic, memory and dense circuit applications. We demonstrate that by using Si epitaxial raised source (S)/drain (D) (SEG) followed by highly doped drain (HDD)-only implantations (I/I), or by using doped-SEG and no I/I: 1) lower off-state current (I OFF) and drain induced barrier lowering effect (DIBL); 2) steeper sub-threshold slope (SS); 3) higher on-state/off-state currents ratio (I ON/I OFF); and 4) higher retention times [for floating body random-access memory (FBRAM) on UTBB] can be obtained, while reducing cost and cycle time with less critical I/I photos. SEG facet formation can be controlled by the spacers shape and epi pre-clean step and its impact on device characteristics for logic and FBRAM applications is also analyzed.

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A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

Cited by 6 publications

References 5 publications

Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Embedding Device Solutions in Engineered Substrates

Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

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