Two- and Three-Dimensional Fully-Depleted Extension-Less Devices for Advanced Logic and Memory Applications

Abstract

In this work we explore the use of extension-less doping schemes for fully-depleted devices [two-dimensional (2D): ultra-thin body and buried-oxide layer (BOX) planar devices (UTBB); three-dimensional (3D): multi-gate field-effect transistor devices with the conduction channels wrapped around silicon (Si) fins (FinFETs) and built on bulk-Si or silicon-on-insulator (SOI) substrates], suitable for advanced logic, memory and dense circuit applications. We demonstrate that by using Si epitaxial raised source (S)/drain (D) (SEG) followed by highly doped drain (HDD)-only implantations (I/I), or by using doped-SEG and no I/I: 1) lower off-state current (I OFF) and drain induced barrier lowering effect (DIBL); 2) steeper sub-threshold slope (SS); 3) higher on-state/off-state currents ratio (I ON/I OFF); and 4) higher retention times [for floating body random-access memory (FBRAM) on UTBB] can be obtained, while reducing cost and cycle time with less critical I/I photos. SEG facet formation can be controlled by the spacers shape and epi pre-clean step and its impact on device characteristics for logic and FBRAM applications is also analyzed.

Junctionless versus inversion-mode lateral semiconductor nanowire transistors

“…With regard to the doping strategy used for the fabrication of these devices, we will focus in this paper on an overview comparison between inversion-mode (IM) FETs built with conventional junctions or an extensionless scheme [20,31,32] versus junctionless (JL) devices [20,26,33]. The latter are especially attractive to consider due to their process simplicity since they do not require source/channel and drain/ channel pn junctions, both of which need nanometer scale control in advanced, scaled IM CMOS technologies.…”

“…As shown earlier in figure 10, JL transistors can have a lower E ox at operating conditions, a value which can be further optimized by tuning of the doping conditions used for the channel of the devices. Regarding IM transistors, reduced E ox values have also been reported for the case of devices built without extensions (extensionless IM (Extless)) [31,32]. These lower E ox FETs are attractive options to consider from a reliability perspective.…”

(Invited) Room Temperature Aging Effect Improvement for Device Stability and Manufacturability of FinFET Technologies

“…However, for device with 24h Q-time (Fig. 4b), O concentration increased significantly in TiAlC film up to 0.9, and it also penetrated into cap TiN and HfO 2 films, causing V t shifts (2,4). In addition, a much lower Al-content bump (ratio ~ 0.25) in TiN capping layer was observed in Fig.…”

“…In FinFET technology with metal/high-K gate, device V t is controlled through effective work function (EWF) engineering by optimal metal layer thickness as well as controlled Aluminum (Al) doping/diffusion within the gate stack (1)(2)(3)(4). The device V t can also be influenced by its architectural elements and process parameters (5) which are supposed to be well controlled during the volume manufacturing.…”

(Invited) Gate-All-Around Nanowire FETs vs. Triple-Gate FinFETs: On Gate Integrity and Device Characteristics

“…GAA-NWFET devices have the potential to offer superior short-channel electrostatic control, and are thus regarded as one of the most promising candidates to further support the CMOS roadmap. In this work, we report a comprehensive evaluation of these two types of device architectures (triple-gate finFET vs. lateral GAA-NWFET) from a device and circuit perspective, focusing on the key topics of gate stack integrity, leakage, reliability and noise performance and on the impact of the process options used, including the pursued doping strategy: inversion-mode (IM) FETs with extensionless (7,12,13) or conventional junctions vs. junctionless (JL) devices (7,14). The latter are especially attractive in terms of their process simplicity since they do not require junctions, and are thus also potentially interesting to use in the context of vertical GAA-NWFETs (15) and in sequential three-dimensional (3D) integration as top-level FETs (16).…”