(Invited) Room Temperature Aging Effect Improvement for Device Stability and Manufacturability of FinFET Technologies

Abstract

In FinFET technology, device threshold voltage (V t ) stability is a pre-requisite for volume manufacturing. Device architectural elements, process parameters and room temperature aging (Q-time) are the main source of V t instability. For the first time, we report a method to minimize V t instability due to Q-time in gate stack work function (n-WF) layer film depositions. Underlying mechanism was investigated using elemental analysis. The optimized n-WF layer recipes were developed that are less sensitive to the Q-time. Device benefits such as T inv scaling and thereby I on -I off performance improvement is demonstrated without compromising the reliability.