(Invited) Gate-All-Around Nanowire FETs vs. Triple-Gate FinFETs: On Gate Integrity and Device Characteristics

Abstract

This work reports a comprehensive evaluation of lateral gate-all-around (GAA) nanowire (NW) FETs vs. triple-gate finFETs, with both types of devices built with various doping schemes, and with GAA-NWFETs outperforming others per footprint. Optimized junctionless (JL) GAA-NWFETs exhibit excellent electrostatics and smaller IOFF values. They also yield ring oscillators with substantially lower power dissipation, while showing considerably longer BTI lifetimes. Improved reliability and increased robustness against process variations in the GAA formation module are also obtained for extensionless vs. reference inversion-mode (IM) FETs built with conventional junctions, at comparable device and circuit performance. JL GAA-NWFET devices also show improved on and off state hot carrier (HC) reliability and reduced LF noise, with some of them also exhibiting smaller subthreshold slope values after HC stress. In addition, further improvements in the noise, reliability and mobility performance of GAA-NWFETs can be obtained by introduction of a TiAl-based EWF-metal in the gate stack.

Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?

“…As a reference, the value for a trigate nFinFET, fabricated with a similar process flow is also given. The following conclusions can be drawn: except for the IM NW devices, lower noise PSD can be found for the GAA transistors compared with FinFETs (FF) [4], [8], [22], [23]. The observed reduction in noise PSD is not orders of magnitude as in other reports and has been related to the preferential conduction inside the uniformly doped nanowire [6].…”

“…The single horizontal NWFETs have been processed on 300 mm diameter SOI substrates as described in detail elsewhere [4], [22], [23]. The fin width was 22-23 nm and the height 30 nm.…”

Atomic Layer Deposition (ALD) of Metal Gates for CMOS

“…The FinFETs have become the mainstream logic devices for a few nodes [52]. The GAA nano-Si wire FETs and Si nano-sheets FETs have been reported by the research teams using industrial processing facility [53][54][55][56][57][58]. The relation between Vt and the work function of the gate electrode for FinFETs with undoped channel is different to that for the planar MOSFETs.…”

Extensive Electrical Characterization Methodology of Advanced MOSFETs Towards Analog and RF Applications

“…either bulk-or SOI-based FinFETs [9,10]). Gate-all-around NanoWire (NW) MOSFETs with the gate completely wrapping around the device body is widely discussed as an ultimate device with an excellent electrostatic control for (sub)-5 nm [11][12][13][14]. Exploitation of 3 rd dimension comes as the new horizon, extending the traditional 2D scaling concept, by increasing the number of devices and their current density per µm 3 instead of µm 2 .…”

“…Their exploitation will be demonstrated on selected study cases of various advanced devices in wide temperature and frequency ranges, performed in our laboratory over the last years . In order to be complete, important works of other groups in the domain of device assessment for analog/RF applications are also listed [3,10,13,23,[79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95].…”