A. De Keersgieter scite author profile

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A. De Keersgieter

Relation between breakdown mode and breakdown location in short channel NMOSFETs and its impact on reliability specifications

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

Scalability of the Si/sub 1-x/Ge/sub x/ source/drain technology for the 45-nm technology node and beyond

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Consistent model for short-channel nMOSFET after hard gate oxide breakdown

Electrical TCAD Simulations of a Germanium pMOSFET Technology

25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions.

Advances on doping strategies for triple-gate finFETs and lateral gate-all-around nanowire FETs and their impact on device performance

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