Advances on doping strategies for triple-gate finFETs and lateral gate-all-around nanowire FETs and their impact on device performance

Veloso, A.; Keersgieter, A. De; Matagne, P.; Horiguchi, N.; Collaert, N.

doi:10.1016/j.mssp.2016.10.018

Cited by 30 publications

(33 citation statements)

References 21 publications

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“…NW FETs are extremely scaled FinFETs [51], [52]. In this case, the channel is fabricated either on an SOI substrate, or free standing by isotropic etching followed by deposition of the gate dielectric and the metal gate [ Fig.…”

Section: Nanowires and 3-d Stackingmentioning

confidence: 99%

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Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Chatzikyriakou

Morgan

Groot

2018

IEEE Trans. Electron Devices

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-From man-made satellites and interplanetary missions to fusion power plants, electronic equipment that needs to withstand various forms of irradiation is an essential part of their operation. Examination of total ionizing dose (TID) effects in electronic equipment can provide a thorough means to predict their reliability in conditions where ionizing dose becomes a serious hazard. In this paper, we provide a historical overview of logic and memory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID. Further to this, we also provide guidelines for hardened device designs and present the cases where hardened alternatives have been implemented and tested in the lab. The technologies that we examine range from silicon-on-insulator and FinFET to 2-D semiconductor transistors and resistive random access memory.Index Terms-2-D semiconductor, carbon, CMOS, deep submicrometer, FinFET, graphene, MoS2, resistive random access memory (RRAM), silicon-on-insulator (SOI), thin film, total ionizing dose (TID), ultrathin buried oxide (UTBOX).

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Section: Nanowires and 3-d Stackingmentioning

confidence: 99%

“…Stacking the NWs in tiers is also an efficient method of device integration, fully 3-D in nature [52]. NWs are stacked on top of each other with each channel being wrapped by a gate oxide stack and the gate.…”

Section: Nanowires and 3-d Stackingmentioning

confidence: 99%

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Chatzikyriakou

Morgan

Groot

2018

IEEE Trans. Electron Devices

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“…One of the critical integration challenges for FinFETs lies with doping, which in fins is significantly different than that in planar devices [31,32]. Three issues are included: (1) the need for conformal doping in the S/D contact and extension regions so that the carrier conduction is uniform in the fin-channel; (2) the tight pitch of the fins limits the beam incidence angles, then the shadowing from neighboring fins has be avoided; (3) damage, accumulation and annealing in high-aspect ratio fins are significantly different from those in planar junctions.…”

Section: Uniform Junction Formation In Finmentioning

confidence: 99%

“…After conventional I/I, an amorphization of the Si fins occurs and later poor re-crystallization is obtained during junction anneal which results in poor dopant activation and defected fins [31]. The implant condition for fin doping can also impact the quality and the growth rate of the S/D epitaxy, which will have implications on the S/D and contact resistance.…”

Section: Uniform Junction Formation In Finmentioning

confidence: 99%

“…The implant condition for fin doping can also impact the quality and the growth rate of the S/D epitaxy, which will have implications on the S/D and contact resistance. Hot I/I with increasing the Si wafer temperature during I/I up to a certain targeted value could be an option to reduce the amorphous depth and fin damage [31,32]. Other innovative doping schemes e.g., solid-source doping, conformal plasma doping, and molecular monolayer doping can be also applied to improve the doping profile.…”

Section: Uniform Junction Formation In Finmentioning

confidence: 99%

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The Challenges of Advanced CMOS Process from 2D to 3D

Radamson

Zhang

et al. 2017

Applied Sciences

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Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

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Width‐Dependent Sheet Resistance of Nanometer‐Wide Si Fins as Measured with Micro Four‐Point Probe

Bogdanowicz

Folkersma

Sergeant

et al. 2017

Physica Status Solidi (a)

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This paper extends the applicability of the micro four-point probe technique from the sheet resistance measurements on large areas toward narrow (<20 nm) semiconducting nanostructures with an elongated fin geometry. Using this technology, it is shown that the sheet resistance of boron-implanted and laser-annealed silicon fins with widths ranging from 500 down to 20 nm rises as the width is reduced. Drift-diffusion simulations show that the observed increase can be partially explained by the carrier depletion induced by interface states at the fin sidewalls.

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Advances on doping strategies for triple-gate finFETs and lateral gate-all-around nanowire FETs and their impact on device performance

Cited by 30 publications

References 21 publications

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

The Challenges of Advanced CMOS Process from 2D to 3D

Width‐Dependent Sheet Resistance of Nanometer‐Wide Si Fins as Measured with Micro Four‐Point Probe

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