Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Chatzikyriakou, Eleni; Morgan, Katrina; Groot, C. H. de

doi:10.1109/ted.2018.2792305

Cited by 18 publications

(8 citation statements)

References 114 publications

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“…I dlin ascends from 2.5 to 3.7 μA/μm at D = 100 krad(Si), and then reaches a plateau with N ot saturating. ON-resistance (R on ) is defined as the resistance of the device at a linear region with V gs = 20 V, which can be briefly expressed as (10) where R ch and R acc are the channel resistance and resistance of accumulation region, respectively; R nwell is the resistance of n-well region; R d is the resistance of drift region; R(D) is the resistance of the extra conduction path induced by TID, as shown in (11).…”

Section: B Mechanism Of I Dlin Increasementioning

confidence: 99%

See 1 more Smart Citation

Improved Model on Buried-Oxide Damage Induced by Total-Ionizing-Dose Effect for HV SOI LDMOS

Yuan

Qiao

et al. 2021

IEEE Trans. Electron Devices

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Section: B Mechanism Of I Dlin Increasementioning

confidence: 99%

“…in space radiation-hardening application [1], [2]. Totalionizing-dose (TID) effect is one of the most common irradiation damages for semiconductor devices applied in space equipment [3]- [10]. For TID effect on low-voltage SOI MOSFET, the damage on buried-oxide (BOX) may lead to the increase of OFF-state leakage and coupling effect [11]- [13].…”

mentioning

confidence: 99%

Improved Model on Buried-Oxide Damage Induced by Total-Ionizing-Dose Effect for HV SOI LDMOS

Yuan

Qiao

et al. 2021

IEEE Trans. Electron Devices

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“…The trapped charges are responsible for a degraded current gain and an increased recombination rate in bipolar transistors, reduced mobility, threshold voltage shifts, an increase of 1/f noise, mismatch and leakage current in MOS transistors. 11,12,14 From a circuit perspective, device TID e↵ects deteriorate circuit behaviour and may lead to a reduced performance to even complete failure in CMOS circuits and systems.…”

Section: Introductionmentioning

confidence: 99%

Low-power electronic technologies for harsh radiation environments

et al. 2021

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Over the past decades, electronic technologies have evolved to serve a wide range of applications, with some necessitating their reliable operation in harsh radiation environments. This perspective article reviews the current landscape in rad-hard electronics, covering the scope of radiation environments, the application needs, the underlying phenomena that impose functional constraints as well as established design methodologies, relying on commercially available technologies (CMOS) for mitigating e↵ects that lead to failure. We further examine the potential of emerging memristive technologies in this field and their properties that render these rad-hard. We also review a variety of rad-hard device designs, rad-mitigation techniques, and experimental procedures for validating the performance of the most promising solutions. Finally, we conclude this article by presenting a roadmap on new concepts and application opportunities enabled by the introduction of novel technologies and designs that can reliably operate under such extreme conditions. topilot upsets that occur on average once in every 200 flight hours, notwithstanding, electrical upsets in automotive electronics and data centers. 3,7 In addition, the solar flares' intense particles and X-rays ionize and increase the density of the low layers of ionosphere, respectively, and interact with the electromagnetic waves resulting into disturbances in the high-frequency radio communication system by fading of the HF signal. 3 These problems eventually a↵ect the stability of the flight system, and tra c operations and navigations both in airspace and on the ground, where safety assurance is of primary importance. Similarly, the operation of nuclear facilities in a safety critical manner is of paramount importance and rad-hard technologies are commonly employed to enhance the overall safety margins. 8 Moreover, radiation e↵ects raise a concern in medical and industrial equipment where X-ray and are used for therapy and diagnostic purposes while in highenergy physics facilities, various particles and photons are generated by the collisions in particle accelerators which pose a severe challenge for the accelerator instrumentation and the radiation detection, data acquisition and communication in the embarked experiments. 9Nevertheless, rad-hard integrated circuit technologies often require additional processing and more complex configurations than the standard fabrication flow that makes the rad-hard electronics, particularly low-power electronic technologies, di cult to keep up with the International Technology Roadmap for Semiconductors (ITRS) guide. 10 This article examines the latest logic and memory design techniques for radiation e↵ect mitigation and presents future trends for rad-hard technologies.

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“…However, there are a large number of cosmic rays, solar electromagnetic radiation, and high-energy charged particles in the space irradiation environment, which have significant impacts on the performance and reliability of electronic devices. In particular, the total ionizing dose (TID) effects can lead to off-state current (Ioff) increase, threshold voltage (Vt) shift, and reliability degradation [6][7][8]. Therefore, to ensure the long-life and reliable operation of spacecrafts, it is necessary to improve the anti-TID performance of semiconductor devices used in space.…”

Section: Introductionmentioning

confidence: 99%

“…In recent years, many scholars have conducted extensive research on the TID effects of nanoscale electronic devices, including 28 nm bulk transistors, 28 nm FD-SOI transistors, and 20 nm UTB-FDSOI devices [8][9][10][11]. Different from conventional planar bulk devices, SOI devices feature an insulating buried oxide (BOX) layer.…”

Section: Introductionmentioning

confidence: 99%

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

Yan

et al. 2020

IEEE Access

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Based on 22 nm ultrathin-body fully depleted silicon-on-insulator (UTB-FDSOI) transistors, we propose a novel structure of buried insulator layer aiming at total ionizing dose (TID) effects mitigation. Using technology computer-aided design (TCAD) tools, we focus on the influences of UTB-FDSOI devices with different structures and parameters on TID effects, such as buried oxide (BOX) layer thickness, buried Si3N4 layer, and electron traps. First, we construct four types of UTB-FDSOI N-type metal-oxide semiconductor (NMOS) devices numerically, in which the novel device features a buried silicon-oxidenitride-oxide-silicon (SONOS) structure. Then, the transfer characteristics and trapped charge distribution of these devices are studied under different irradiation doses. It is known that a thinner BOX layer could lead to slighter TID effects, and the buried nitride layer and the electron traps could reduce the TID-induced leakage current (Ioff). Employing these optimization structures for TID effects hardness, the innovative transistor shows much better resistance against TID effects compared to the conventional FDSOI transistors. In addition, the threshold voltage of the novel device could be increased by applying appropriate bias conditions, similar to those of programming SONOS memory, so that the Ioff caused by TID irradiation further decreases. These results provide useful guidance for designers to achieve TID effects mitigation of SOI devices.

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Total Ionizing Dose Hardened and Mitigation Strategies in Deep Submicrometer CMOS and Beyond

Cited by 18 publications

References 114 publications

Improved Model on Buried-Oxide Damage Induced by Total-Ionizing-Dose Effect for HV SOI LDMOS

Improved Model on Buried-Oxide Damage Induced by Total-Ionizing-Dose Effect for HV SOI LDMOS

Low-power electronic technologies for harsh radiation environments

Simulation of Total Ionizing Dose (TID) Effects Mitigation Technique for 22 nm Fully-Depleted Silicon-on-Insulator (FDSOI) Transistor

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