The Challenges of Advanced CMOS Process from 2D to 3D

Abstract

Abstract:The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.

Low‐Temperature Wafer‐Scale Deposition of Continuous 2D SnS2 Films

“…Low processing temperatures are also desirable to ensure compatibility with the wide range of substrates and other thin film layers needed to realize various applications. In addition, many industrially relevant device structures, such as FETs and random‐access memory cells, are highly 3D, and thus difficult to coat uniformly . These issues pose heavy demands on film deposition and have so far not been met for 2D SnS 2 .…”

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

“…Comparing with remote plasma and QALE, the selectivity to SiO2 is lower, but it has obvious advantages in etching anisotropy, which is crucial to control the accuracy of the final thickness of inner spacer. 3 Data of special method-typical remote downstream plasma 4 Data of special method-typical quasi-atomic layer etching 5 Related data are unknown…”

Accurate Models for Evaluating the Direct Conducted and Radiated Emissions from Integrated Circuits

“…From Figure 7b it results that the crosstalk noise is completely negligible, thanks to already-mentioned design guidelines adopted for the multilayered structure. After computing the S-parameters, the admittance matrix has been derived from (2) and then synthesized with a low-order approximation as in (3). The matrix entries in (3) have been implemented through the equivalent circuits in Figure 3.…”

“…The current technology trends push towards the realization of integrated circuits (ICs) characterized by smaller size, lower power supply voltages, and higher operating frequencies [1]. In addition, conventional solutions are no longer applicable and, therefore, a great amount of effort is given to finding new materials (such as the use of nanomaterials [2]) and/or new architectures (e.g., the 3D integration [3]).…”