Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors

Abstract

Stacked SiGe/Si structures are widely used as the units for gate-all-around nanowire transistors (GAA NWTs) which are a promising candidate beyond fin field effective transistors (FinFETs) technologies in near future. These structures deal with a several challenges brought by the shrinking of device dimensions. The preparation of inner spacers is one of the most critical processes for GAA nano-scale transistors. This study focuses on two key processes: inner spacer film conformal deposition and accurate etching. The results show that low pressure chemical vapor deposition (LPCVD) silicon nitride has a good film filling effect; a precise and controllable silicon nitride inner spacer structure is prepared by using an inductively coupled plasma (ICP) tool and a new gas mixtures of CH2F2/CH4/O2/Ar. Silicon nitride inner spacer etch has a high etch selectivity ratio, exceeding 100:1 to Si and more than 30:1 to SiO2. High anisotropy with an excellent vertical/lateral etch ratio exceeding 80:1 is successfully demonstrated. It also provides a solution to the key process challenges of nano-transistors beyond 5 nm node.

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

“…During the fabrication of stacked GAA Si NW/NS MOSFETs, a multi-step high temperature annealing process is needed, such as shallow trench isolation (STI) annealing and source drain (SD) activation. The high temperature processes would result in a fast atom diffusion in multi-layer GeSi/Si stacks, and the abrupt interfaces among the multi-layer GeSi/Si stacks layers would be destroyed, which would affect the structure, morphology, and quality of the formed Si NS channels [ 19 , 20 , 21 ]. In order to study the influence of annealing temperature on the GeSi selective etch, the samples with GeSi/Si stack arrays were annealed at 650 °C, 700 °C, 750 °C, 800 °C, 850 °C, and 900 °C for 30 s, respectively, in N 2 atmosphere using rapid thermal annealing (RTA) equipment.…”

Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs

“…In this context, our simulation studies were performed under the situation shown in Figure 1e. Summary of device fabrication processing with 3-dimensional graphics has been reported in previous works, in detail [16,17]. Figure 2 provides a schematic diagram of an NS FET for mechanical simulation.…”

State of the Art and Future Perspectives in Advanced CMOS Technology

“…The thicker thicknesses will increase the resistance between S/D when the device is turned on [ 191 , 192 ]. Inner spacers have greater challenges than conventional spacers where a higher etching selection ratio and etching accuracy are required [ 195 ]. In addition to the good dielectric properties, the corrosion resistance of the inner wall material is also very important, because the sidewall material needs to undergo nanowire release in the nanowire preparation process, and it needs to be resistant to erosion in the arounding process.…”

“…Li et al studied the conformal deposition of inner spacer using LPCVD, and the precise dry etching using an innovative gas mixture of CH 2 F 2 /CH 4 /O 2 /Ar. The structures are shown in Figure 37 [ 195 ].…”

“…In addition to the above-mentioned SiN materials, high selectivity for precise etching of SiO 2 [224], and new channel materials GaN [225], InGaAs [226], and MoS 2 [227] are all worthy of attention. [195].…”