Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs

Lee, Khwang-Sun; Park, Jun-Young

doi:10.3390/electronics10121395

Cited by 12 publications

(9 citation statements)

References 23 publications

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“…In addition, with respect to source/drain (S/D) modules, the contact depth as well as inner spacer thickness needs to be optimized [ 8 , 9 ]. It should be noted in particular that, unlike bulk FinFETs, which have already been mass produced, NS FETs have a parasitic channel underneath the first floor nanosheet [ 10 , 11 , 12 , 13 ].…”

Section: Introductionmentioning

confidence: 99%

N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

Lee

Park

2022

Micromachines

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This paper proposes a simplified fabrication processing for nanosheet Field-Effect Transistors (FETs) part of beyond-3-nm node technology. Formation of the ground plane (GP) region can be replaced by an epitaxial grown doped ultra-thin (DUT) layer on the starting wafer prior to Six/SiGe1-x stack formation. The proposed process flow can be performed in-situ, and does not require changing chambers or a high temperature annealing process. In short, conventional processes such as ion implantation and subsequent thermal annealing, which have been utilized for the GP region, can be replaced without degrading device performance.

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Section: Introductionmentioning

confidence: 99%

N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

Lee

Park

2022

Micromachines

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“…The NS FET has three suspended channels composed of silicon which are surrounded by a highk and metal gate. The gate length (L G ), channel width (W NS ), nanosheet thickness (T NS ), and nanosheetto-nanosheet vertical space (V SPC ) were 12 nm, 30 nm, 5 nm, and 15 nm, respectively [13]. The SiO 2 and HfO 2 interlayers of 1 nm and 3 nm, respectively, were deposited on suspended nanosheets as the gate dielectric.…”

Section: Device Structure and Simulation Methodologymentioning

confidence: 99%

“…Gate length, L G TiAlC 12 nm [20] Channel width, W NS Si 30 nm [13] Nanosheet thickness, T NS Si 5 nm [13] Inner…”

Section: Parameters Materials Valuesmentioning

confidence: 99%

Vacuum Inner Spacer to Improve Annealing Effect during Electro-Thermal Annealing of Nanosheet FETs

2022

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Electro-thermal annealing (ETA) in a MOSFET utilizes Joule heating. The high-temperature heat effectively cures gate dielectric damages induced by electrical stresses or ionizing radiation. However, even though ETA can be used to improve the reliability of logic and memory devices, applying ETA in state-of-the-art field-effect transistors (FETs) such as nanosheet FETs (NS FETs) has not yet been demonstrated. This paper addresses the heat distribution characteristic of an NS FET considering the application of ETA, using 3D simulations. A vacuum inner spacer is newly proposed to improve annealing effects during ETA. In addition, evaluations of the device scaling and annealing effect were performed with respect to gate length, nanosheet-to-nanosheet vertical space, and inner spacer thickness. Guidelines for ETA in NS FETs can be provided on the basis of the results.

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Section: Process Challenges For 2dm Nsfetsmentioning

confidence: 99%

“…Even with the ideal channel release process, the risk of vertical deflection induced through the mass of 2DM channels must be taken into account. [ 73 ] The maximum deflection appears in the center of the channel and, according to the material mechanics, typically exhibits an inverse dependence on the flexural rigidity ( D ), which can be described as follows:

D = E I and I = 1 / 12 W_{normalC}_{H} T_{C H}^{3}

where I , W CH , T CH , and E represent the area moment of inertia, channel width, channel thickness, and Young's modulus, respectively. [ 74 ] D highly depends on T CH (Figure 7f), and thus, down to the monolayer limit, the selection of 2DMs with proper E and ultrascaled feature size is critical for optimizing the bending deflection.…”

Section: Process Challenges For 2dm Nsfetsmentioning

confidence: 99%

2D Materials‐Based Static Random‐Access Memory

Liu

Wan

et al. 2022

Advanced Materials

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2DM)-based field-effect transistors (FETs) with ultrathin bodies and superior electrostatics have great potential for application in ultra-high-density integrated circuits. [2,3] 2D transition-metal dichalcogenide (TMDC) semiconductors, such as MoS 2 and WSe 2 , with adequate bandgaps maintaining low off-state leakage current (I off ), are promising channel materials for highly scaled transistors. [4] Static random-access memory (SRAM) is a volatile storage technology that requires a constant power supply to store data. Unlike dynamic random-access memory, SRAM does not require periodic refreshing, because the flip-flop-based latching circuit can store data in bistable states. [5,6] SRAM, with its rapid access time and low power consumption, has become indispensable in memory technology. For improved computing performance, central processing units are now equipped with large-capacity cache memory (one type of fast SRAM) to hold copies of data from the main memory blocks and reduce the latency of data access. Because the computing cores constantly access on-chip SRAM caches, improvement in the density, performance, and energy efficiency of SRAM caches is essential for future high-performance computing applications. [7][8][9] A typical SRAM comprises six metal-oxide-semiconductor FETs (MOSFETs), including two pull-up, two pull-down, and two pass-gate MOSFETs. Consequently, SRAM faces the same challenges in maintaining low power consumption, high performance, and strong reliability as MOSFET scaling, resulting from the physical limitation of the silicon channel material. When the silicon thickness scales down to sub-10 nm, rough surface scattering and the large leakage current markedly degrade device performance. [3,10] Hence, 2D semiconductor materials with ultrathin bodies and smooth surfaces are potential candidates for replacing silicon at advanced technology nodes (TNs).2DM-based SRAM cells have been studied to generate superior performance. The six-transistor (6T) WSe 2 -based SRAM cells have been demonstrated to operate at a low supply voltage (V dd ) of 0.8 V. [11] Furthermore, the two-transistor two-resistor MoS 2 -based SRAM cells exhibit lower power consumption and higher write stability than the 6T WSe 2 -based SRAM cells. [12] In addition, layered and monolithic 3D integrated 2DM SRAM cells have superior area efficiency and adequate stability. [13,14] This study provides insight into designing high-performance 2D transition-metal dichalcogenide semiconductors, such as MoS 2 and WSe 2 , with adequate bandgaps are promising channel materials for ultrascaled logic transistors. This scalability study of 2D material (2DM)-based field-effect transistor (FET) and static random-access memory (SRAM) cells analyzing the impact of layer thickness reveals that the monolayer 2DM FET with superior electrostatics is beneficial for its ability to mitigate the read-write conflict in an SRAM cell at scaled technology nodes (1-2.1 nm). Moreover, the monolayer 2DM SRAM exhibits lower cell read access time and write time th...

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Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs

Cited by 12 publications

References 23 publications

N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

Vacuum Inner Spacer to Improve Annealing Effect during Electro-Thermal Annealing of Nanosheet FETs

2D Materials‐Based Static Random‐Access Memory

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