N-Type Nanosheet FETs without Ground Plane Region for Process Simplification

Abstract

This paper proposes a simplified fabrication processing for nanosheet Field-Effect Transistors (FETs) part of beyond-3-nm node technology. Formation of the ground plane (GP) region can be replaced by an epitaxial grown doped ultra-thin (DUT) layer on the starting wafer prior to Six/SiGe1-x stack formation. The proposed process flow can be performed in-situ, and does not require changing chambers or a high temperature annealing process. In short, conventional processes such as ion implantation and subsequent thermal annealing, which have been utilized for the GP region, can be replaced without degrading device performance.

Vacuum Inner Spacer to Improve Annealing Effect during Electro-Thermal Annealing of Nanosheet FETs

“…Hence, a V SPC narrower than 15 nm would be preferred for a better annealing effect of NS FETs. This tendency coincides with the development trend of current NS FETs toward a narrower V SPC for better packing density [26].…”

Structure of an In Situ Phosphorus-Doped Silicon Ultrathin Film Analyzed Using Second Harmonic Generation and Simplified Bond-Hyperpolarizability Model

“…Although device scaling approaches have reached an extreme level, suppressing short-channel effects by using fin FETs is still difficult. As a solution for 3D structure devices, FETs composed of multiple nanosheets with a gate-all-around (GAA) structure are good candidates for replacing fin FETs at the 5 nm technology node and beyond [ 5 , 6 ]. One of the most important achievements in 3D device manufacturing is the production of high and stable doping in the source and drain (S/D) region [ 1 , 3 ].…”

“…P-doped Si S/D that uses the in situ-doped epitaxy process has been developed because this process flow accepts a more accurate dopant concentration without additional thermal treatment [ 8 , 9 ]. However, in situ doping layers grown on the Si surface exhibit inherent defects that correlate with the growth condition and dopant density [ 5 ] due to a solubility limitation [ 10 , 11 ]. Investigations on P-doped Si films have suggested that donor–vacancy complexes can cause some of the doped P atoms to not emit free carriers; this phenomenon is called electrical deactivation [ 12 , 13 , 14 ].…”

Editorial for the Special Issue on Recent Advances in Thin Film Electronic Devices

“…Interestingly, some novel processes relating thin film electronic devices were reported in this Special Issue [14,15]. K. S. Lee employed a process simplification for n-type nanosheet FETs without a ground plane region [14]; the proposed flow could be performed in situ, without the requirement of changing chambers or a high-temperature annealing process.…”

“…Interestingly, some novel processes relating thin film electronic devices were reported in this Special Issue [14,15]. K. S. Lee employed a process simplification for n-type nanosheet FETs without a ground plane region [14]; the proposed flow could be performed in situ, without the requirement of changing chambers or a high-temperature annealing process. In addition, X. Ding et al successfully realized the efficient multi-material structured thin film transfer to elastomers for stretchable electronic devices by combining bench-top thin film structuring with solvent-assisted lift-off methods [15].…”