Mechanical stress is demonstrated in the fabrication process of nanosheet FETs. In particular, unwanted mechanical instability stemming from gravity during channel-release is covered in detail by aid of 3-D simulations. The simulation results show the physical weakness of suspended nanosheets and the impact of nanosheet thickness. Inner spacer engineering based on geometry and elastic property are suggested for better mechanical stability. The formation of wide contact area between inner spacer and nanosheet, as well as applying rigid spacer dielectric material, are preferred.
This paper proposes a simplified fabrication processing for nanosheet Field-Effect Transistors (FETs) part of beyond-3-nm node technology. Formation of the ground plane (GP) region can be replaced by an epitaxial grown doped ultra-thin (DUT) layer on the starting wafer prior to Six/SiGe1-x stack formation. The proposed process flow can be performed in-situ, and does not require changing chambers or a high temperature annealing process. In short, conventional processes such as ion implantation and subsequent thermal annealing, which have been utilized for the GP region, can be replaced without degrading device performance.
In contrast to conventional forming gas annealing (FGA), high-pressure deuterium annealing (HPD) shows a superior passivation of dangling bonds on the Si/SiO2 interface. However, research detailing the process optimization for HPD has been modest. In this context, this paper demonstrates the iterative impact of HPD for the better fabrication of semiconductor devices. Long-channel gate-enclosed FETs are fabricated as a test vehicle. After each cycle of the annealing, device parameters are extracted and compared depending on the number of the HPD. Based on the results, an HPD condition that maximizes on-state current (ION) but minimizes off-state current (IOFF) can be provided.
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