Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

Abstract

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

Fabrication of High-Mobility Si0.7Ge0.3 Channel FinFET for Optimization of Device Electrical Performance

“…Meanwhile, an extra GP doping implantation with a dosage of 5e 13 cm −2 prior to the Si 0.7 Ge 0.3 epitaxial growth was also employed to further reduce its SS and leakage performance. 18,21 This is because counter doping of the parasitic channel can increase its threshold voltage and minimize the effect of the parasitic channel. The electrical performance of the Si 0.7 Ge 0.3 FinFET device was clearly improved after the Al 2 O 3 /HfO 2 bi-layer dielectric, O 3 passivation, and GP implantation online, as shown in Fig.…”

Germanium Nanosheet-FETs Scaled to Subnanometer Node Utilizing Monolithically Integrated Lattice Matched Ge/AlAs and Strained Ge/InGaAs

“…3(d) which uses a lattice matched Ge/AlAs structure. The NSFET fabrication process involves four key steps: (i) multilayer epitaxy with alternate layers of channel material (Si or Ge) and sacrificial layer (SiGe or here, AlAs) which defines the thickness, composition and quality of the of the NSFET channel, (ii) fin pattering and definition of channel length (L CH ) and channel width (W CH ), (iii) dummy gate and outer spacer deposition for anchoring of the NS followed by source and drain epitaxial growth, and (iv) etching of the sacrificial layer followed by NS release [2], [23]. Utilizing the Si/SiGe multilayer structure (shown in Fig.…”

A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation

“…According to previous studies, available processes for the isotropic selective etching of SiGe include wet etching [ 18 ], plasma dry etching developed in reactive ion etching [ 19 , 20 ] and remote plasma dry etching [ 21 ]. Wet etching is unstable in a high-aspect-ratio structure due to the influence of the capillary effect [ 22 ]. Another issue is that the capillary forces inherent in wet etching may cause adjacent nanosheets to stick together [ 23 ].…”