A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation

Sun, Xin; Wang, Dawei; Qian, Lewen; Liu, Tao; Yang, Jingwen; Chen, Kun; Wang, Luyu; Huang, Ziqiang; Xu, Min; Wang, Chen; Wu, Chunlei; Xu, Shengjun; Zhang, David Wei

doi:10.3390/nano13030504

Cited by 4 publications

(7 citation statements)

References 30 publications

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“…Furthermore, the FBFET structures are compatible with CMOS top-down fabrication techniques. The nano-scale silicon channels of the FBFETs can be achieved by stacking Si/SiGe multilayers [24]. The selective removal of the sacrificial SiGe layers enables the devices to be formed as a vertical nanosheet gateall-around structure.…”

Section: Resultsmentioning

confidence: 99%

Generation and Storage of Random Voltage Values via Ring Oscillators Comprising Feedback Field-Effect Transistors

Son,

Jeon,

Cho

et al. 2024

Nanomaterials

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In this study, we demonstrate the generation and storage of random voltage values using a ring oscillator consisting of feedback field-effect transistors (FBFETs). This innovative approach utilizes the logic-in-memory function of FBFETs to extract continuous output voltages from oscillatory cycles. The ring oscillator exhibited uniform probability distributions of 51.6% for logic 0 and 48.4% for logic 1. The generation of analog voltages provides binary random variables that are stored for over 5000 s. This demonstrates the potential of the ring oscillator in advanced physical functions and true random number generator technologies.

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Section: Resultsmentioning

confidence: 99%

Generation and Storage of Random Voltage Values via Ring Oscillators Comprising Feedback Field-Effect Transistors

Son,

Jeon,

Cho

et al. 2024

Nanomaterials

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“…The cross section of the Si/SiGe stacked multilayer was analyzed by a high-resolution transmission electron microscope (HRTEM). The process flow and the test pattern for the channel release used in this work have already been described elsewhere [ 18 ]. Figure 3 shows a schematic diagram of cavity etch using the direct etching process and the cyclic etching process.…”

Section: Methodsmentioning

confidence: 99%

“…However, this process has a “top-down” effect, which is unacceptable for the inner spacer module. In our previous work [ 18 ], an NF 3 -based remote plasma dry etching process was proposed, which achieved the channel release of nanosheets with multiple widths from 30 nm to 80 nm with little Si loss.…”

Section: Introductionmentioning

confidence: 99%

A Comprehensive Study of NF3-Based Selective Etching Processes: Application to the Fabrication of Vertically Stacked Horizontal Gate-All-around Si Nanosheet Transistors

Sun,

Li,

Qian

et al. 2024

Nanomaterials

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In this paper, we demonstrate a comprehensive study of NF3-based selective etching processes for inner spacer formation and for channel release, enabling stacked horizontal gate-all-around Si nanosheet transistor architectures. A cyclic etching process consisting of an oxidation treatment step and an etching step is proposed and used for SiGe selective etching. The cyclic etching process exhibits a slower etching rate and higher etching selectivity compared to the direct etching process. The cycle etching process consisting of Recipe 1, which has a SiGe etching rate of 0.98 nm/cycle, is used for the cavity etch. The process achieved good interlayer uniformity of cavity depth (cavity depth ≤ 5 ± 0.3 nm), while also obtaining a near-ideal rectangular SiGe etch front shape (inner spacer shape = 0.84) and little Si loss (0.44 nm@ each side). The cycle etching process consisting of Recipe 4 with extremely high etching selectivity is used for channel release. The process realizes the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss. In addition, a selective isotropic etching process using NF3/O2/Ar gas mixture is used to etch back the SiN film. The impact of the O2/NF3 ratio on the etching selectivity of SiN to Si and the surface roughness of SiN after etching is investigated. With the introduction of O2 into NF3/Ar discharge, the selectivity increases sharply, but when the ratio of O2/NF3 is up to 1.0, the selectivity tends to a constant value and the surface roughness of SiN increases rapidly. The optimal parameter is O2/NF3 = 0.5, resulting in a selectivity of 5.4 and a roughness of 0.19 nm.

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“…The formation of inner spacer requires lateral etching of SiGe about 5 nm, which demands for extreme etching process control and high precision [4].The uniform and rectangular SiGe contour is desired to protect drain and source during channel release. Channel release requires high-selectivity etching, and since the Si channel is formed after etching, it is necessary to reduce etching damage of the Si surface to ensure device electrical performance [5]. Nowadays, there is no unified solution for the above processes, and reports on comparisons between different solutions are scarce.…”

Section: Introductionmentioning

confidence: 99%

Study of selective dry etching Si0.7Ge0.3 with different plasma source in process of gate-all-around FET

Liu,

Yang,

et al. 2024

Advanced Etch Technology and Process Integration for Nanopatterning XIII

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The lateral gate-all-around (GAA) field effect transistor is considered to be the most promising candidate for the next generation of logic devices at the 3nm technology node and beyond. SiGe plays an important role as a sacrificial layer in the GAA device, which requires isotropic etching, and the quality of the etching has a critical impact on the device performance. However, there is no definite scheme in the industry for the choice of etching method. In this paper, we choose two etching methods-ICP(Inductively coupled Plasma) and RPS (Remote Plasma Source) etching according to the presence or absence of particle incidence. The profile and etching effect of the two etching methods are analyzed by PEGASUS simulation software. The presence or absence of particle incidence has different effects on the damage of the structure, the inconsistency of etching amount and the reflection of the particles on the Si surface. Compared with ICP etching, the optimization of RPS etching on etching damage and etch amount consistency is verified by TEM and roughness characterization . And through the extraction of MOSCAP capacitance, it is found that the density of interface states(Dit) after ICP etching is 3.5 times higher than that of RPS etching.

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A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation

Cited by 4 publications

References 30 publications

Generation and Storage of Random Voltage Values via Ring Oscillators Comprising Feedback Field-Effect Transistors

Generation and Storage of Random Voltage Values via Ring Oscillators Comprising Feedback Field-Effect Transistors

A Comprehensive Study of NF3-Based Selective Etching Processes: Application to the Fabrication of Vertically Stacked Horizontal Gate-All-around Si Nanosheet Transistors

Study of selective dry etching Si0.7Ge0.3 with different plasma source in process of gate-all-around FET

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