Fabrication of High-Mobility Si_0.7Ge_0.3 Channel FinFET for Optimization of Device Electrical Performance

Abstract

The fabrication process and electrical performance optimization of a high-mobility Si 0.7 Ge 0.3 channel FinFET device were systematically explored. A high-quality of Si 0.7 Ge 0.3 fin formation on Si substrates with shallow trench isolation-last (STI-last) scheme was first realized by a direct fin patterning and low-temperature STI annealing just after a blanket Si 0.7 Ge 0.3 film growth on Si substrate. To solve the process compatibility issue of the Si 0.7 Ge 0.3 fin, a new spacer etching process with CH 3 F/CF 4 -based plasma was developed because the existing spacer etching process is only appropriate for the Si fin and causes serious loss of the Si 0.7 Ge 0.3 fin due to its low selectivity. Moreover, rapid thermal annealing at 850 °C for 30 s was chosen as the optimal source/ drain (dopant activation process to maintain the thermal stability of the Si 0.7 Ge 0.3 fin. In-situ O 3 passivation, Al 2 O 3 /HfO 2 bi-layer gate dielectric, and an extra ground-plane doping implantation were identified as key factors for improving the electrical performance of the Si 0.7 Ge 0.3 channel FinFET device. Finally, a Si 0.7 Ge 0.3 channel FinFET device with a subthrehold swing of 87 mV dec −1 and an I on /I off ratio of 4e 5 was fabricated successfully using the proposed processes.