In this paper, a fabrication technique of Si 0.5 Ge 0.5 Fin for the high mobility channel FinFET device is systematically investigated. Although the shallow trench isolation (STI) densification temperature is already reduced from 1050 °C to 850 °C, the Si 0.5 Ge 0.5 Fin with the STI annealing first approach still suffers from thermal instability and micro trench issue. It is no possible to further reduce the STI densification temperature using the traditional furnace annealing for the Si 0.5 Ge 0.5 Fin, because the STI densification process of 750 °C also faces the same issue with an unacceptable STI wet etching rate. Thus, a spike annealing of 1050 °C is employed to maintain Si 0.5 Ge 0.5 Fin stability and render the STI etching rate acceptable. The spike annealing treated Si 0.5 Ge 0.5 Fin maintains a better profile than the furnace annealing sample, but it still faces the micro trench issue after the STI recess. This is because the Si 0.5 Ge 0.5 Fin is already oxidized and SiGeO x has a higher etching rate than STI oxide. Finally, a novel STI recess first process with an extra SiN capping is developed to solve both the thermal instability and the micro trench issue, and a minor Si 0.5 Ge 0.5 Fin loss with sharp Si 0.7 Ge 0.3 SRB/Si 0.5 Ge 0.5 interfaces for the STI last scheme is realized by utilizing this novel STI recess first process.
In this paper, to solve the epitaxial thickness limit and the high interface trap density of SiGe channel Fin field effect transistor (FinFET), a four-period vertically stacked SiGe/Si channel FinFET is presented. A high crystal quality of four-period stacked SiGe/Si multilayer epitaxial grown with the thickness of each SiGe layer less than 10 nm is realized on a Si substrate without any structural defect impact by optimizing its epitaxial grown process. Meanwhile, the Ge atomic fraction of the SiGe layers is very uniform and its SiGe/Si interfaces are sharp. Then, a vertical profile of the stacked SiGe/Si Fin is achieved with HBr/O2/He plasma by optimizing its bias voltage and O2 flow. After the four-period vertically stacked SiGe/Si Fin structure is introduced, its FinFET device is successfully fabricated under the same fabrication process as the conventional SiGe FinFET. And it attains better drive current Ion, subthreshold slope (SS) and Ion/Ioff ratio electrical performance compared with the conventional SiGe channel FinFET, whose Fin height of SiGe channel is almost equal to total thickness of SiGe in the four-period stacked SiGe/Si channel FinFET. This may be attributed to that the four-period stacked SiGe/Si Fin structure has larger effective channel width (Weff) and may maintain a better quality and surface interfacial performance during the whole fabrication process. Moreover, Si channel of the stacked SiGe/Si channel turning on first also may have contribution to its better electrical properties. This four-period vertically stacked SiGe/Si channel FinFET device has been demonstrated to be a practical candidate for the future technology nodes.
In this study, the thermal stability of a Si0.7Ge0.3/Si stacked multilayer for gate-all-around (GAA) MOSFETS is systematically investigated. Rapid thermal annealing (RTA) treatments at temperatures ranging from 800 °C to 1050 °C are performed on the Si0.7Ge0.3/Si stacked multilayer samples. Compared with the as-grown sample, the RTA-treated (800 °C–900 °C) Si0.7Ge0.3/Si stacked multilayer samples attain good crystal quality, a sharp interface between Si0.7Ge0.3 and Si, and minor diffusion of Ge. Furthermore, owing to the rapid diffusion of Ge, the thickness of Si0.7Ge0.3 increases by ∼6 nm and the Ge concentration of Si0.7Ge0.3 reduces by ∼3% as the annealing temperature increases to 950 °C. The interfaces of the Si0.7Ge0.3/Si stacked multilayer disappear and finally behave like a homogeneous SiGe alloy as the annealing temperature further increases to 1000 °C or 1050 °C. Therefore, for thermal stability, the highest tolerable temperature of 900 °C is proposed for the Si0.7Ge0.3/Si stacked multilayer for the fabrication of the GAA device.
A high crystalline quality of SiGe fin with an Si-rich composition area using the replacement fin processing is systematically demonstrated in this paper. The fin replacement process based on a standard FinFET process is developed. A width of less than 20-nm SiGe fin without obvious defect impact both in the direction across the fin and in the direction along the fin is verified by using the high angle annular dark field scanning transmission electron microscopy and the scanning moiré fringe imaging technique. Moreover, the SiGe composition is inhomogenous in the width of the fin. This is induced by the formation of {111} facets. Due to the atomic density of the {111} facets being higher, the epitaxial growth in the direction perpendicular to these facets is slower than in the direction perpendicular to {001}. The Ge incorporation is then higher on the {111} facets than on the {001} facets. So, an Si-rich area is observed in the central area and on the bottom of SiGe fin.
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