Fabrication technique of the Si_0.5Ge_0.5 Fin for the high mobility channel FinFET device

Abstract

In this paper, a fabrication technique of Si 0.5 Ge 0.5 Fin for the high mobility channel FinFET device is systematically investigated. Although the shallow trench isolation (STI) densification temperature is already reduced from 1050 °C to 850 °C, the Si 0.5 Ge 0.5 Fin with the STI annealing first approach still suffers from thermal instability and micro trench issue. It is no possible to further reduce the STI densification temperature using the traditional furnace annealing for the Si 0.5 Ge 0.5 Fin, because the STI densification process of 750 °C also faces the same issue with an unacceptable STI wet etching rate. Thus, a spike annealing of 1050 °C is employed to maintain Si 0.5 Ge 0.5 Fin stability and render the STI etching rate acceptable. The spike annealing treated Si 0.5 Ge 0.5 Fin maintains a better profile than the furnace annealing sample, but it still faces the micro trench issue after the STI recess. This is because the Si 0.5 Ge 0.5 Fin is already oxidized and SiGeO x has a higher etching rate than STI oxide. Finally, a novel STI recess first process with an extra SiN capping is developed to solve both the thermal instability and the micro trench issue, and a minor Si 0.5 Ge 0.5 Fin loss with sharp Si 0.7 Ge 0.3 SRB/Si 0.5 Ge 0.5 interfaces for the STI last scheme is realized by utilizing this novel STI recess first process.

Process Corresponding Implications Associated with a Conclusive Model-Fit Current-Voltage Characteristic Curves

“…Therefore by using the same skill, all the parameters in Equations ( 1) and ( 2) are determined to fit the measured characteristic curves except the ones in Figure 2a,b. where the two transistors, denoted by W110L100 (Fin width = 110 nm, Channel length = In addition, all determined k N 's may be specifically listed as in Tables 1-3 at different sizes and at different V G 's [12]. In the modified conventional formula in Equations ( 1) and ( 2), k N is supposed to be inversely proportional to the channel length.…”

“…On the other hand, the mobility of silicon channel may be promoted by even 2.5 to 4 times as SiGe is technically and sophisticatedly introduced stack by stack. The above advanced techniques and other options are definitely promising and achievable, making FinFET continuously popular as currently [6][7][8][9][10][11][12].…”

Si0.5Ge0.5 Channel FinFET Preparation on an In Situ Doped SiGe SRB and Its Electrical Characteristics Optimization

“…Then, the introduction of Si 0.5 Ge 0.5 channel was realized by Si 0.5 Ge 0.5 /SiGe SRB fin patterning and low temperature STI process based on STI last scheme. 9 In addition, to further improve the electrical characteristics of the device, a S/D NiPt silicide process and an in situ ozone oxidation followed by HfO 2 /Al 2 O 3 bi-layer high-k dielectric deposition were employed. In particular, to ensure the formation of the low resistivity phase NiSi (Ge) while avoiding excessive solidification in silicide process, 13 the unreacted NiPt was selectively removed with HNO 3 : HCI (1:3) after the first rapid thermal annealing (RTP) treatment of 310 °C for 60 s. Then, a second RTP treatment of 500 °C for 10 s was performed to induce the change of the remaining Ni 2 Si (Ge) convert to the desired NiSi(Ge).…”

“…7 In our previous work, we investigated the epitaxial growth of strain relaxed buffer (SRB) layer and Si 0.5 Ge 0.5 channel introduction technique based on STI last scheme. 8,9 However, it is necessary to further overcome some other challenges, such as leakage of parasitic sub-fin channel, interface state density (Dit) of SiGe channel, and large source-drain series resistance of fin structure. [10][11][12] Therefore, for Si 0.5 Ge 0.5 channel FinFET, the fabrication of the device and its electrical characteristics optimization need to be further investigated, as relatively few studies have been reported so far.…”

Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics

“…The low-Ge-content SiGe channel will be implemented firstly on the FinFET owing to its advantages of higher hole mobility, better negative bias temperature instability (NBTI) reliability than silicon and more compatible with present silicon platform [ 4 , 5 ]. So far, a SiGe channel can be integrated in FinFET architectures in multiple ways, e.g., by shallow trench isolation (STI) last scheme [ 6 ] or by STI first strategy [ 7 ] or epitaxial cladding of Si Fins [ 8 ]. However, a high quality of low-Ge-content SiGe epitaxial grown on Si substrate is still a challenge task to solve the epitaxial thickness limit of SiGe film and the threading dislocations (TD) defects.…”