2022
DOI: 10.1016/j.mssp.2021.106373
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Si0.5Ge0.5 channel introduction technique for the preparation of high mobility FinFET device

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Cited by 3 publications
(3 citation statements)
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“…I DS of 421 µA/µm under V DS = V GS = −0.8 V, I ON /I OFF ratio of ∼ 3×10 5 , and SS of 64 mV/dec are obtained. Comparing with the conventional Si 0.7 Ge 0.3 FinFET with optimized electrical performance reported earlier, [16] its SS can be reduced by 24%, improving from 87 mV/dec to 64 mV/dec. These mentioned results indicate that a stronger gate control capability to the Si 0.7 Ge 0.3 channel is attained after adopting a narrowed Si 0.7 Ge 0.3 fin by utilizing a precise cyclic wet treatment process.…”
Section: Narrowed Si 07 Ge 03 Finfet Devicementioning
confidence: 72%
See 1 more Smart Citation
“…I DS of 421 µA/µm under V DS = V GS = −0.8 V, I ON /I OFF ratio of ∼ 3×10 5 , and SS of 64 mV/dec are obtained. Comparing with the conventional Si 0.7 Ge 0.3 FinFET with optimized electrical performance reported earlier, [16] its SS can be reduced by 24%, improving from 87 mV/dec to 64 mV/dec. These mentioned results indicate that a stronger gate control capability to the Si 0.7 Ge 0.3 channel is attained after adopting a narrowed Si 0.7 Ge 0.3 fin by utilizing a precise cyclic wet treatment process.…”
Section: Narrowed Si 07 Ge 03 Finfet Devicementioning
confidence: 72%
“…The key electrical property of the narrowed Si 0.7 Ge 0.3 FinFET is compared with those of some reported SiGe FinFET/GAA devices. [3,[17][18][19][20][21][22][23] Figure 7 summarizes the SS-I ON /I OFF benchmark of the reported SiGe FinFET/GAA devices. The I ON /I OFF ratio of the narrowed Si 0.7 Ge 0.3 FinFET is higher than the average value of the comparison groups.…”
Section: Narrowed Si 07 Ge 03 Finfet Devicementioning
confidence: 99%
“…In many previous works, SiGe channel material is mainly used in PMOS rather than NMOS to enhance the hole mobility in PMOS devices [9][10][11]. The layer effects in SiGe channel are also studied [12,13]. The drawback of the SiGe channel in NMOS devices is the electron mobility degradation due to its high interface trap states [14,15], which can be eliminated in technology computer-aided design (TCAD) simulations [16].…”
Section: Introductionmentioning
confidence: 99%