Fabrication and selective wet etching of Si0.2Ge0.8/Ge multilayer for Si0.2Ge0.8 channel gate-all-around MOSFETs

Liu, Haoyan; Li, Yongliang; Cheng, Xiaohong; Zan, Ying; Lu, Yihong; Wang, Guilei; Li, Junjie; Kong, Zhenzhen; Ma, Xueli; Yang, Hong; Luo, Jun; Wang, Wenwu

doi:10.1016/j.mssp.2020.105397

Cited by 9 publications

(4 citation statements)

References 3 publications

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“…As can been seen from the images, the thicknesses of GeSi and Si layers are about 17 nm and 12 nm, respectively, and the component of multi-stack GeSi/Si has a good period property, which means the multi-layer GeSi/Si films have good uniformity and abrupt GeSi/Si interfaces. 6,32 Figs. 2c and 2d show the microscope and SEM images of the high-efficiency hybrid pattern formed by using SIT and photo lithography technology to form the nanoscale fin and large-size LPs at the same time, where the SiNx spacer HMs and photoresist for fin and LPs patterns, respectively.…”

Section: Resultsmentioning

confidence: 99%

“…With continuous minimization of Si integrated circuits (ICs) along the Moore's law, metal oxide semiconductor field effect transistors (MOSFETs) are becoming smaller in size and consuming less in power. [1][2][3][4][5][6][7][8][9] Although three-dimensional (3D) bulk-Si fin field effect transistor (FinFET) has been applied into the IC mass production from 22 nm to 5 nm nodes for a long time, it is becoming more challenging for them to meet the basic requirements of the performance and the power consumption specifications for the next generation ICs. [10][11][12][13][14] Attributed to its high integration density, superiority in the control of short channel effects (SCEs), high performance and large flexibility in circuits design, as well as perfect process compatibility with current FinFET manufacture process, [15][16][17] the vertically-stacked gate-all-around (GAA) Si nanosheets (NSs) FET is believed as one of the most promising solutions to be applied into the mainstream IC manufacture while the technology is shrunk beyond 3nm node.…”

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confidence: 99%

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Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

Tian

Zhang

et al. 2022

ECS J. Solid State Sci. Technol.

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In order to improve the driving ability of vertically-stacked gate-all-around (GAA) Si nanosheets (NSs) devices, a high-efficiency hybrid pattern technique with the SiNx spacer-image transfer and conventional photolithography pattern was proposed and implemented to form size-enlarged landing pads (LPs) on nanometer-scale fins at the same time, which increase the volumes of electrical conductance pathway between NS channel and source and drain (SD) electrodes with high process efficiency and compatibility with traditional mass production technology. Due to introduced new structures, the parasitic resistance of the devices is reduced by 99.8% compared with those w./o. LPs. Therefore, ~3 times and ~2 times driving current enhancements for 500 nm gate length n-type and p-type MOSFETs are obtained, respectively. The results indicate the proposed GAA NS FET fabrication process with LPs by high-efficiency hybrid pattern technique a promising solution for improving the device driving ability for stacked GAA Si NSs devices in future.

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Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 99%

Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

Tian

Zhang

et al. 2022

ECS J. Solid State Sci. Technol.

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“…As can be seen from Figure 7 b, the physical L g is 25.8 nm and the stacked GAA Si NSs device is well fabricated, because the SD fin, spacer, and gate trench are well protected with conformal ILD0 material, allowing the Si NS channels and conformal HK/MG GAA structure to be preserved after the final process steps. As can be seen from Figure 7 c, there are four uniform stacked Si NS channels formed and thickness of the NSs is about 6 nm, implying the well-controlled Si NS release and fabrication processes [ 22 , 23 , 24 ]. The Si NSs channel were surrounded by the conformal ALD multilayer HKMG stacks to form GAA structure, which could provide a good gate control ability to the ultrathin Si NS channels.…”

Section: Resultsmentioning

confidence: 99%

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

Zhang

et al. 2021

Nanomaterials

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In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

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“…As a result, the simulate values are 40-50 mV/V, which is larger than the experimental data. Neverthe qualitative performance is well reproduceable [194]. [192].…”

Section: Epitaxy Of Gesi and Ge For Channel Regionmentioning

confidence: 91%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Fabrication and selective wet etching of Si0.2Ge0.8/Ge multilayer for Si0.2Ge0.8 channel gate-all-around MOSFETs

Cited by 9 publications

References 3 publications

Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

Improving Driving Current with High-Efficiency Landing Pads Technique for Reduced Parasitic Resistance in Gate-All-Around Si Nanosheet Devices

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

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