Electrical TCAD Simulations of a Germanium pMOSFET Technology

Hellings, Geert; Eneman, G.; Krom, R.; Jaeger, B. De; Mitard, J.; Keersgieter, A. De; Hoffmann, T.; Meuris, Marc; Meyer, K. De

doi:10.1109/ted.2010.2060726

Cited by 94 publications

(35 citation statements)

References 21 publications

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“…The electron-phonon interaction term |M k 0 | 2 and the phonon energyhω k 0 for Ge are calculated and given as: 4.85 × 10 −32 eV 2 m 3 and 8.6 meV, respectively, using the parameters from [11]. The Sentaurus simulations for the calculation of the SRH recombination contribution used the following carrier lifetime parameters: τ max,n = 4 · 10 −5 s and τ max, p = 4·10 −5 s [20]. The nonparabolicity factor for the conduction band of germanium is taken as 0.85 eV −1 [21].…”

Section: Simulation Parameters and Resultsmentioning

confidence: 99%

Quantum Mechanical Study of the Germanium Electron–Hole Bilayer Tunnel FET

Alper

Lattanzio

Michielis

et al. 2013

IEEE Trans. Electron Devices

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The electron-hole bilayer tunnel field-effect transistor (EHBTFET) is an electronic switch that uses 2-D-2-D sub-band-to-sub-band tunneling (BTBT) between electron and hole inversion layers and shows significant subthermal swing over several decades of current due to the step-like 2-D density of states behavior. In this paper, EHBTFET has been simulated using a quantum mechanical model. The model results are compared against transactions on computer-aided design simulations and remarkable differences show the importance of quantum effects and dimensionality in this device. Ge EHBTFET with channel thickness of 10 nm results as a promising device for low supply voltage, subthreshold logic applications, with a super steep switching behavior featuring SS avg ∼ 40 mV/dec up to V DD . Furthermore, it has been demonstrated that high ON current levels (∼40 µA/µm) can be achieved due to the transition from phonon-assisted BTBT to direct BTBT at higher biases.Index Terms-2-D-2-D tunneling, band-to-band tunneling (BTBT), density of states (DOS), electron-hole bilayer tunnel field-effect transistor (EHBTFET), germanium, quantum mechanical (QM) simulation, subthreshold slope, tunnel field-effect transistor (TFET).

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Section: Simulation Parameters and Resultsmentioning

confidence: 99%

Quantum Mechanical Study of the Germanium Electron–Hole Bilayer Tunnel FET

Alper

Lattanzio

Michielis

et al. 2013

IEEE Trans. Electron Devices

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“…The tunneling masses mc and mv for silicon were tuned in [15], to calibrate the model by comparing to experimental data for tunneling diodes [16]. All the material parameters related to Ge for the Si 0.6 Ge 0.4 source in n-type Tunnel FETs were taken from [17]. The effect of the large tensile stress (+3GPa) used in p-type TFETs was included through an adjustment of the effective energy bandgap through physically based bandstructure calculations, as discussed more thoroughly in [18].…”

Section: Device Structure Device Level Modeling and Device-circuit Smentioning

confidence: 99%

Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits

Alioto

Esseni

2014

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design

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In this paper, the potential of Tunnel FETs (TFETs) for ultra-low power operation is investigated in the context of digital circuits operating below 500 mV. A comparative analysis of TFETs and SOI CMOS in 32 nm technology is performed through deviceand circuit-level simulations, based on a unitary simulation framework where all devices are fairly designed for the same (low) voltage range and the same device-level targets.The performance is evaluated through figures of merit at device and circuit level, quantifying the impact of each device parameter on the performance. The analysis considers both the nominal corner and the impact of the variations of various device parameters, which is evaluated through sensitivity analysis. The results permit to identify the most critical TFET parameters subject to variations that require finer control at process level, to keep circuit-level variations within reasonable bounds. From the perspective of technology scaling, the analysis shows that TFETs can significantly relax the physical-level constraints on gate pitch, thereby mitigating the printability issues in 32-nm technologies and beyond.

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“…Finally, Hellings et al discussed Ge device simulation model parameters for carrier generation/recombination, mobility, and interface traps [121]. They calibrated models to measurements, which they used to make device predictions.…”

Section: Modelling and Projectionsmentioning

confidence: 99%

Processing of germanium for integrated circuits

Duffy¹,

Shayesteh²,

Yu³

2014

Turk J Phys

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Abstract:In this review paper the authors will focus on Ge processing for integrated circuits. The key areas that require the most attention are substrates and integration, gate dielectrics, and access resistance. We will discuss each of these topics in turn, while also reviewing the most scaled Ge field-effect-transistor devices, and consider how modelling activities have matured for Ge in recent years.

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Electrical TCAD Simulations of a Germanium pMOSFET Technology

Cited by 94 publications

References 21 publications

Quantum Mechanical Study of the Germanium Electron–Hole Bilayer Tunnel FET

Quantum Mechanical Study of the Germanium Electron–Hole Bilayer Tunnel FET

Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits

Processing of germanium for integrated circuits

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