Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Shino, T.; Kusunoki, N.; Higashi, Taneaki; Ohsawa, Takashi; Fujita, Katsushi; Hatsuda, K.; Ikumi, N.; Matsuoka, F.; Kajitani, Yoji; Fukuda, R.; Watanabe, Yoshinori; Minami, Y.; Sakamoto, Atsushi; Nishimura, Jun; Nakajima, Masayuki; Morikado, M.; Inoh, K.; Hamamoto, T.; Nitayama, A.

doi:10.1109/iedm.2006.346846

Cited by 28 publications

(5 citation statements)

References 3 publications

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“…Some kinds of capacitor-less DRAM cell have been proposed and developed [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. Floating body cell (FBC) is a promising candidate in view of its simple structure and scalability.…”

Section: Introductionmentioning

confidence: 99%

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Hamamoto

Ohsawa

2009

Solid-State Electronics

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Section: Introductionmentioning

confidence: 99%

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Hamamoto

Ohsawa

2009

Solid-State Electronics

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“…The development of the FBC technology is being attentively followed by the IC community. Recently a 128Mb FBC was reported [27] and its scalability to 32nm has been proven [28]. Further, the FBC concept has been proven to work as well for FinFET architecture [29].…”

Section: Capacitor Less Dramsmentioning

confidence: 99%

Embedding Device Solutions in Engineered Substrates

Mazuré¹

2007

ECS Trans.

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A review of the advances in Smart Cut engineered substrates and the impact on device architecture and IC design is given. Primarily focusing on CMOS applications, mobility enhancing substrates, fully depleted device compatibility to SOI product capability and multi-gate FinFETs will be reviewed. IntroductionA simple structure like silicon on insulator (SOI) has allowed the IC industry to optimize the MOSFET architecture by reducing parasitic capacitances to the substrate, cutting device leakage, improving device speed while reducing power consumption, decreasing considerably soft error rate, and so forth. The benefits and potential of SOI have been known since the 60's [1]. The real issue for an industrial SOI development was SOI substrate availability and wafer quality. This roadblock vanished with the invention of Smart Cut TM [2,3], a single crystal thin layer transfer technology. The simplicity of this technique underlines simultaneously the power and potential of Smart Cut technology and explains why it has become today the industrial standard for thin layer transfer [4].Smart Cut technology consists in defining a splitting region within the donor substrate by ion implantation (e.g. H), which allows a thin film to transfer to a handle wafer after bonding and splitting. The thickness removed from the donor wafer is negligible compared to the total wafer thickness. Consequently, the donor wafer can be reused many times. A range of 10 nm up to a few 10 3 nm in top Si and buried oxide (BOX) thickness is easily covered by this technology.Beyond SOI, Smart Cut technology opens the door to substrate engineering, i.e. the capability to design new substrates tailored to specific applications [5]. It is possible to amplify certain device properties while weakening others by combining different materials or crystal orientations, adding strained layers, or simply creating a new composite substrate.High performance ICs continue to be the driver for a specialized family of advanced substrates. Ultra-thin (UT) SOI, mobility enhancing substrates like strained SOI (sSOI) in addition to local strain techniques [6], as well as improved thermal dissipation to reduce the impact of hot spots on MOSFET performance are among the most obvious engineered substrate solutions [5]. Direct silicon Bonding (DSB) adds a high-end mobility enhancing substrate to the bulk Si IC architectures [7]. Non-planar device architectures like FinFETs take advantage of the buried oxide or nitride as an etch stop for fin height definition, thus reducing fin variability [5].A review of the advances in Smart Cut engineered substrates and the impact on device performance and IC design is given below. High Performance SubstratesBeyond the 90nm technology node, the electron and hole mobility enhancement have become essential to assure device performance increase while scaling. Two approaches are clearly identified: strained silicon, and dual crystal orientation surfaces. The first one is evolutionary and takes advantage of strain inducing CMOS processes whi...

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“…The large volume capacitor of the one transistor (1T)-one capacitor (1C) DRAM has limited its further applications in advanced memory fields with shrinking cell size [1][2][3]. Various capacitor-less memory devices have thus been proposed to avoid the problems associated with the scaling of a capacitor and achieve high memory density [4][5][6][7][8]. One promising candidate is the semi-floating gate transistor (SFGT) with an embedded tunneling field-effect transistor (TFET) [8,9].…”

Section: Introductionmentioning

confidence: 99%

A Semi-Floating Gate Memory with Tensile Stress for Enhanced Performance

et al. 2019

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With the continuous scaling down of devices, traditional one-transistor one-capacitor dynamic random access memory (1T-1C DRAM) has encountered great challenges originated from the large-volume capacitor and high leakage current. A semi-floating gate transistor has been proposed as a capacitor-less memory with ultrafast speed and silicon-compatible technology. In this work, a U-shaped semi-floating gate memory with strain technology has been demonstrated through TCAD simulation. Ultra-high operation speed on a timescale of 5 ns at low operation voltages (≤ 2.0 V) has been obtained. And the tensile stress induced in its channel region by using contact etch stop layer (Si3N4 capper layer) was found to significantly improve the drain current by 12.07%. Furthermore, this device demonstrated a favorable retention performance with a retention time over 1 s, and its immunity to disturbance from bit-line has also been investigated that could maintain data under the continuous worst writing disturbance operation over 10 ms.

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Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Cited by 28 publications

References 3 publications

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Embedding Device Solutions in Engineered Substrates

A Semi-Floating Gate Memory with Tensile Stress for Enhanced Performance

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