A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes

Shiga, H.; Takashima, D.; Shiratake, S.; Hoya, K.; Miyakawa, T.; Ogiwara, R.; Fukuda, R.; Takizawa, Ryosuke; Hatsuda, K.; Matsuoka, F.; Nagadomi, Yasushi; Hashimoto, Daisuke; Nishimura, H.; Hioka, Takeshi; Doumae, Sumiko; Shimizu, S.; Kawano, M.; Taguchi, T.; Watanabe, Yoshihiro; Fujii, Shuso; Ozaki, T.; Kanaya, Haruichi; Kumura, Y.; Shimojo, Y.; Yamada, Yuji; Minami, Y.; Shuto, S.; Yamaguchi, Koji; Yamazaki, S.; Kunishima, I.; Hamamoto, T.; Nitayama, A.; Furuyama, T.

doi:10.1109/isscc.2009.4977509

Cited by 21 publications

(8 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The simulators simulate ARM processor with additional memory access instructions. For this target system, the parameters of FRAM are obtained from [21]. A read operation to FRAM register takes 0.5ns and a write to register takes 5ns.…”

Section: Methodsmentioning

confidence: 99%

Non-volatile registers aware instruction selection for embedded systems

Xie

Pan

et al. 2014

2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications

View full text Add to dashboard Cite

It is common that embedded systems are powered by limited and unstable power supply. In order to improve the reliability of embedded systems against unstable power supply, non-volatile memory (e.g. FRAM) based registers are proposed for embedded processors. FRAM-based registers have many advantages over traditional CMOS-based volatile registers such as non-volatility and power-economy. However, similar to other non-volatile memories (NVM), write operations to FRAM consume more time and power compared with read operations and limit the lifetime of the registers. Existing compiler optimization techniques never take the writes to registers into consideration. Therefore, code generated by a traditional compiler has an adverse effect on processors with non-volatile registers.This paper aims at improving the lifetime and efficiency of non-volatile registers based embedded processors by generating NV register friendly code. To achieve the goal, in this paper, we investigate the usage of memory access instructions and propose the NV Register Aware Instruction Selection (NAIS) algorithm to reduce the write operations on non-volatile registers. According to the experimental results, the proposed algorithm can reduce the writes on NV registers by 66.89% on average when compared with GCC [1]. Thus the lifetime of NV registers is extended to 2 times as long as before on average. The time cost is reduced by 56.68% and the energy consumption is reduced by 59.76% on average.

show abstract

Section: Methodsmentioning

confidence: 99%

Non-volatile registers aware instruction selection for embedded systems

Xie

Pan

et al. 2014

2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications

View full text Add to dashboard Cite

show abstract

“…At the time of writing, the largest FeRAM memory chip demonstrated in literature is a 128 Mbit chain-FeRAM from Toshiba Corporation, built in 0.13μm process technology [187]. The memory cell size in this demonstration was 0.45μm×0.56μm= 0.252μm 2 , with a cell charge of about ∼ 13 fC and a cell signal of ∼ 100 mV.…”

Section: Overview Of Flash Memory and Other Leading Contenders 11mentioning

confidence: 99%

Phase Change Memory: From Devices to Systems

Qureshi

Gurumurthi

Rajendran³

2011

Synthesis Lectures on Computer Architecture

View full text Add to dashboard Cite

“…An additional scaling limit is that the ferroelectric material in FeRAM will lose its ferroelectric characteristic at a very thin thickness, and thus creates an obstacle for scaling up the density. As a result, improvements in the FeRAM density are relatively slow compared with that of flash memory, and the maximum capacity that is currently possible with FeRAM are 128 Mb and 4 Mb at the laboratory level [90] and industrial level [91] respectively, which is much lower than that of flash memory.…”

Section: Ferroelectric Random Access Memorymentioning

confidence: 99%

Physical principles and current status of emerging non-volatile solid state memories

Wang

Yang

Wen

2015

Electron. Mater. Lett.

View full text Add to dashboard Cite

Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for the next generation of data-storage devices based on a comparison of their performance.

show abstract

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes

Cited by 21 publications

References 3 publications

Non-volatile registers aware instruction selection for embedded systems

Non-volatile registers aware instruction selection for embedded systems

Phase Change Memory: From Devices to Systems

Physical principles and current status of emerging non-volatile solid state memories

Contact Info

Product

Resources

About