Scaling enhances intrinsic transistor performance and degrades interconnects. As the technology steps into nanometer era, global interconnects are becoming bottleneck for overall chip performance. In this paper, we show package level interconnects are an effective alternative for on-chip global wiring. These interconnects behave as LC transmission lines and can be exploited for their near speed of light transmission and low attenuation characteristics. We compare performancebandwidth, bandwidth density, latency and power consumptionof the package level transmission lines with conventional on-chip global interconnects for different ITRS technology nodes. Based on these results, we show package level interconnects are well suited for power demanding low latency applications and we analyze different interconnect options like memory buses, long inter tile interconnects, clock and power distribution.
A 576 Mb DRAM is implemented with 16 serial links at 10.3125Gbps. Using careful memory/SerDes/package codesign, the system achieves 14.5ns latency and 24.75GByte/s read/write bandwidth. It achieves SRAM-like random access by using logic-compatible 65nm GP embedded DRAM and small 36 Kb sub-arrays with hidden refresh.
Power distribution and signal transmission are becoming key limiters for chip performance in nanometer era. These issues can be simultaneously addressed by designing transmission lines in power grids. The transmission lines are well suited for high quality intra-chip signal transmission at multi gigabit data rates. By having signal lines between the power grids, the VDD and GND lines in the grid can be exploited as return paths besides being used for regular power distribution. This approach also improves wiring density. In this paper, we rigorously analyze and discuss the design considerations for laying transmission lines in power grids. We also present design oriented modeling methods in 2D and 3D geometry. We show how the grid modeling complexity is simplified. We experimentally validate our results with fabricated test structures. We also show VDD lines in the grid act as good return path without external decoupling capacitors in our design. Further we discuss substrate effects and deduce guidelines for designing power grid transmission lines on a low resistive silicon substrate.
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