Analysis and Modeling of Power Grid Transmission lines

Abstract

Power distribution and signal transmission are becoming key limiters for chip performance in nanometer era. These issues can be simultaneously addressed by designing transmission lines in power grids. The transmission lines are well suited for high quality intra-chip signal transmission at multi gigabit data rates. By having signal lines between the power grids, the VDD and GND lines in the grid can be exploited as return paths besides being used for regular power distribution. This approach also improves wiring density. In this paper, we rigorously analyze and discuss the design considerations for laying transmission lines in power grids. We also present design oriented modeling methods in 2D and 3D geometry. We show how the grid modeling complexity is simplified. We experimentally validate our results with fabricated test structures. We also show VDD lines in the grid act as good return path without external decoupling capacitors in our design. Further we discuss substrate effects and deduce guidelines for designing power grid transmission lines on a low resistive silicon substrate.

CMOS Compatible Anodization Process for Low Cost High Density Capacitors

“…Anodic oxide processing also takes part in chip and device integration. For instance, several references report the use of anodic layer for MOS transistor gate oxide (4)(5), or for its integration in a variety of systems such as electrowetting-on-dielectric structures (EWOD) (6), humidity sensors (7), bacteria detection (8) or power grid transmission lines (9). With recent development of integrated three-dimensional (3D) devices such as high density Metal-Insulator-Metal (MIM) capacitors (10), it is an attractive solution to deposit conformal oxide (11) adapted to high aspect ratio structures (Figure 1).…”