Wafer-level package interconnect options

Balachandran, Jayaprakash; Brebels, S.; Carchon, G.; Kuijk, Maarten; Raedt, W. De; Nauwelaers, Bart; Beyne, Eric

doi:10.1109/tvlsi.2006.878229

Cited by 14 publications

(4 citation statements)

References 25 publications

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“…An RDL is a thick plated metal layer with superior electrical characteristics vs. typical metal layers [4] (Table II). Today, RDLs are processed by the packaging houses rather than foundries.…”

Section: A Commodity Enabling Technologiesmentioning

confidence: 99%

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An RDL-configurable 3D memory tier to replace on-chip SRAM

Facchini

Marchal

Catthoor

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked dies (tiers). This allows redesigning the memory tier as a configurable product to be used in multiple system designs. Previously proposed dynamic re-configurable solutions demonstrate strong dependence between read latency and dimensions of the mapped memory, leading to potential performance limitations. In this paper we propose a one-time configurable memory tier designed to minimize the performances overhead due to the commodity. Flexible configuration is enabled by smart memory macros and I/Os organization and a customizable redistribution layer routing . With respect to the dynamic re-configurability, the proposed design offers up to 40% faster access time, while saving more than 10% of energy per access. In addition production cost trade offs are analyzed.

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Section: A Commodity Enabling Technologiesmentioning

confidence: 99%

“…As a result, they are processed at relatively low cost, but with limited precision (pitch limited to 10 μm). [4] 15/mm * 2/mm * 10 ** 5 Metal 2 -7 250/mm *** 400/mm *** 0.26 *** 0.14*** * = estimation based on similar technology measurements ** = target/assumption *** = approximated values from TSMC90nmG…”

Section: A Commodity Enabling Technologiesmentioning

confidence: 99%

An RDL-configurable 3D memory tier to replace on-chip SRAM

Facchini

Marchal

Catthoor

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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“…3D wafer level integration has been a key technology to microelectronic industries and it is the best for high density and high performance device applications. [1][2][3][4] Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration compared to die-to-die, die-to-wafer, or package-to-package due to high volume manufacturing, smaller package size, and no need for known good die. Especially for the high density and high performance, the wafer stacking with a metallic bonding is necessary and Cu-to-Cu wafer bonding is without doubt a key process to be developed.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Challenges of Cu-to-Cu Wafer Bonding

Kang¹,

Lee²,

Kim³

et al. 2012

Journal of the Microelectronics and Packaging Society

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The demand for 3D wafer level integration has been increasing significantly. Although many technical challenges of wafer stacking are still remaining, wafer stacking is a key technology for 3D integration due to a high volume manufacturing, smaller package size, low cost, and no need for known good die. Among several new process techniques Cu-to-Cu wafer bonding is the key process to be optimized for the high density and high performance IC manufacturing. In this study two main challenges for Cu-to-Cu wafer bonding were evaluated: misalignment and bond quality of bonded wafers. It is demonstrated that the misalignment in a bonded wafer was mainly due to a physical movement of spacer removal step and the bond quality was significantly dependent on Cu bump dishing and oxide erosion by Cu CMP.

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“…The advantages of 3D technologies enable the future applications of integrated circuit industries and open various product options in bio-chip, MEMS chip and traditional IC chip such as processors and memories. However, in addition to processing challenges explained elsewhere [1][2][3][4][5][6], there are still other technological limitations to be resolved in 3D technologies, for example heat extraction, power delivery, design and methodology, testing and reliability. And in the case of wafer stacking technology compared to other stacking technologies, compound yield loss can be a major issue in the manufacturing point of view.…”

Section: Introductionmentioning

confidence: 99%